1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30// Korey Sewell
31
32////////////////////////////////////////////////////////////////////
33//
34// Memory-format instructions
35//
36
37output header {{
38 /**
39 * Base class for general Mips memory-format instructions.
40 */
41 class Memory : public MipsStaticInst
42 {
43 protected:
44 /// Memory request flags. See mem_req_base.hh.
45 Request::Flags memAccessFlags;
46
47 /// Displacement for EA calculation (signed).
48 int32_t disp;
49
50 /// Constructor
51 Memory(const char *mnem, MachInst _machInst, OpClass __opClass)
52 : MipsStaticInst(mnem, _machInst, __opClass),
53 disp(sext<16>(OFFSET))
54 {
55 }
56
57 std::string generateDisassembly(
58 Addr pc, const SymbolTable *symtab) const override;
59 };
60
61 /**
62 * Base class for a few miscellaneous memory-format insts
63 * that don't interpret the disp field
64 */
65 class MemoryNoDisp : public Memory
66 {
67 protected:
68 /// Constructor
69 MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
70 : Memory(mnem, _machInst, __opClass)
71 {
72 }
73
74 std::string generateDisassembly(
75 Addr pc, const SymbolTable *symtab) const override;
76 };
77}};
78
79
80output decoder {{
81 std::string
82 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
83 {
84 return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
85 flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
86 }
87
88 std::string
89 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
90 {
91 return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
92 flags[IsFloating] ? 'f' : 'r',
93 flags[IsFloating] ? FD : RD,
94 RS, RT);
95 }
96
97}};
98
99output header {{
100 uint64_t getMemData(ExecContext *xc, Packet *packet);
101
102}};
103
104output exec {{
105 /** return data in cases where there the size of data is only
106 known in the packet
107 */
108 uint64_t getMemData(ExecContext *xc, Packet *packet) {
109 switch (packet->getSize())
110 {
111 case 1:
112 return packet->getLE<uint8_t>();
113
114 case 2:
115 return packet->getLE<uint16_t>();
116
117 case 4:
118 return packet->getLE<uint32_t>();
119
120 case 8:
121 return packet->getLE<uint64_t>();
122
123 default:
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30// Korey Sewell
31
32////////////////////////////////////////////////////////////////////
33//
34// Memory-format instructions
35//
36
37output header {{
38 /**
39 * Base class for general Mips memory-format instructions.
40 */
41 class Memory : public MipsStaticInst
42 {
43 protected:
44 /// Memory request flags. See mem_req_base.hh.
45 Request::Flags memAccessFlags;
46
47 /// Displacement for EA calculation (signed).
48 int32_t disp;
49
50 /// Constructor
51 Memory(const char *mnem, MachInst _machInst, OpClass __opClass)
52 : MipsStaticInst(mnem, _machInst, __opClass),
53 disp(sext<16>(OFFSET))
54 {
55 }
56
57 std::string generateDisassembly(
58 Addr pc, const SymbolTable *symtab) const override;
59 };
60
61 /**
62 * Base class for a few miscellaneous memory-format insts
63 * that don't interpret the disp field
64 */
65 class MemoryNoDisp : public Memory
66 {
67 protected:
68 /// Constructor
69 MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
70 : Memory(mnem, _machInst, __opClass)
71 {
72 }
73
74 std::string generateDisassembly(
75 Addr pc, const SymbolTable *symtab) const override;
76 };
77}};
78
79
80output decoder {{
81 std::string
82 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
83 {
84 return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
85 flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
86 }
87
88 std::string
89 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
90 {
91 return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
92 flags[IsFloating] ? 'f' : 'r',
93 flags[IsFloating] ? FD : RD,
94 RS, RT);
95 }
96
97}};
98
99output header {{
100 uint64_t getMemData(ExecContext *xc, Packet *packet);
101
102}};
103
104output exec {{
105 /** return data in cases where there the size of data is only
106 known in the packet
107 */
108 uint64_t getMemData(ExecContext *xc, Packet *packet) {
109 switch (packet->getSize())
110 {
111 case 1:
112 return packet->getLE<uint8_t>();
113
114 case 2:
115 return packet->getLE<uint16_t>();
116
117 case 4:
118 return packet->getLE<uint32_t>();
119
120 case 8:
121 return packet->getLE<uint64_t>();
122
123 default:
|
127 return 0;
128 }
129 }
130
131
132}};
133
134def template LoadStoreDeclare {{
135 /**
136 * Static instruction class for "%(mnemonic)s".
137 */
138 class %(class_name)s : public %(base_class)s
139 {
140 public:
141
142 /// Constructor.
143 %(class_name)s(ExtMachInst machInst);
144
145 Fault execute(ExecContext *, Trace::InstRecord *) const override;
146 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
147 Fault completeAcc(Packet *, ExecContext *,
148 Trace::InstRecord *) const override;
149 };
150}};
151
152
153def template LoadStoreConstructor {{
154 %(class_name)s::%(class_name)s(ExtMachInst machInst)
155 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
156 {
157 %(constructor)s;
158 }
159}};
160
161def template LoadExecute {{
162 Fault %(class_name)s::execute(ExecContext *xc,
163 Trace::InstRecord *traceData) const
164 {
165 Addr EA;
166 Fault fault = NoFault;
167
168 if (this->isFloating()) {
169 %(fp_enable_check)s;
170
171 if(fault != NoFault)
172 return fault;
173 }
174
175 %(op_decl)s;
176 %(op_rd)s;
177 %(ea_code)s;
178
179 if (fault == NoFault) {
180 fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
181 %(memacc_code)s;
182 }
183
184 if (fault == NoFault) {
185 %(op_wb)s;
186 }
187
188 return fault;
189 }
190}};
191
192
193def template LoadInitiateAcc {{
194 Fault %(class_name)s::initiateAcc(ExecContext *xc,
195 Trace::InstRecord *traceData) const
196 {
197 Addr EA;
198 Fault fault = NoFault;
199
200 if (this->isFloating()) {
201 %(fp_enable_check)s;
202
203 if(fault != NoFault)
204 return fault;
205 }
206
207 %(op_src_decl)s;
208 %(op_rd)s;
209 %(ea_code)s;
210
211 if (fault == NoFault) {
212 fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);
213 }
214
215 return fault;
216 }
217}};
218
219def template LoadCompleteAcc {{
220 Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
221 Trace::InstRecord *traceData) const
222 {
223 Fault fault = NoFault;
224
225 if (this->isFloating()) {
226 %(fp_enable_check)s;
227
228 if(fault != NoFault)
229 return fault;
230 }
231
232 %(op_decl)s;
233 %(op_rd)s;
234
235 getMem(pkt, Mem, traceData);
236
237 if (fault == NoFault) {
238 %(memacc_code)s;
239 }
240
241 if (fault == NoFault) {
242 %(op_wb)s;
243 }
244
245 return fault;
246 }
247}};
248
249def template StoreExecute {{
250 Fault %(class_name)s::execute(ExecContext *xc,
251 Trace::InstRecord *traceData) const
252 {
253 Addr EA;
254 Fault fault = NoFault;
255
256 %(fp_enable_check)s;
257 %(op_decl)s;
258 %(op_rd)s;
259 %(ea_code)s;
260
261 if (fault == NoFault) {
262 %(memacc_code)s;
263 }
264
265 if (fault == NoFault) {
266 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
267 NULL);
268 }
269
270 if (fault == NoFault) {
271 %(postacc_code)s;
272 }
273
274 if (fault == NoFault) {
275 %(op_wb)s;
276 }
277
278 return fault;
279 }
280}};
281
282
283def template StoreFPExecute {{
284 Fault %(class_name)s::execute(ExecContext *xc,
285 Trace::InstRecord *traceData) const
286 {
287 Addr EA;
288 Fault fault = NoFault;
289
290 %(fp_enable_check)s;
291 if(fault != NoFault)
292 return fault;
293 %(op_decl)s;
294 %(op_rd)s;
295 %(ea_code)s;
296
297 if (fault == NoFault) {
298 %(memacc_code)s;
299 }
300
301 if (fault == NoFault) {
302 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
303 NULL);
304 }
305
306 if (fault == NoFault) {
307 %(postacc_code)s;
308 }
309
310 if (fault == NoFault) {
311 %(op_wb)s;
312 }
313
314 return fault;
315 }
316}};
317
318def template StoreCondExecute {{
319 Fault %(class_name)s::execute(ExecContext *xc,
320 Trace::InstRecord *traceData) const
321 {
322 Addr EA;
323 Fault fault = NoFault;
324 uint64_t write_result = 0;
325
326 %(fp_enable_check)s;
327 %(op_decl)s;
328 %(op_rd)s;
329 %(ea_code)s;
330
331 if (fault == NoFault) {
332 %(memacc_code)s;
333 }
334
335 if (fault == NoFault) {
336 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
337 &write_result);
338 }
339
340 if (fault == NoFault) {
341 %(postacc_code)s;
342 }
343
344 if (fault == NoFault) {
345 %(op_wb)s;
346 }
347
348 return fault;
349 }
350}};
351
352def template StoreInitiateAcc {{
353 Fault %(class_name)s::initiateAcc(ExecContext *xc,
354 Trace::InstRecord *traceData) const
355 {
356 Addr EA;
357 Fault fault = NoFault;
358
359 %(fp_enable_check)s;
360 %(op_decl)s;
361 %(op_rd)s;
362 %(ea_code)s;
363
364 if (fault == NoFault) {
365 %(memacc_code)s;
366 }
367
368 if (fault == NoFault) {
369 fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
370 NULL);
371 }
372
373 return fault;
374 }
375}};
376
377
378def template StoreCompleteAcc {{
379 Fault %(class_name)s::completeAcc(Packet *pkt,
380 ExecContext *xc,
381 Trace::InstRecord *traceData) const
382 {
383 return NoFault;
384 }
385}};
386
387def template StoreCondCompleteAcc {{
388 Fault %(class_name)s::completeAcc(Packet *pkt,
389 ExecContext *xc,
390 Trace::InstRecord *traceData) const
391 {
392 Fault fault = NoFault;
393
394 %(fp_enable_check)s;
395 %(op_dest_decl)s;
396
397 uint64_t write_result = pkt->req->getExtraData();
398
399 if (fault == NoFault) {
400 %(postacc_code)s;
401 }
402
403 if (fault == NoFault) {
404 %(op_wb)s;
405 }
406
407 return fault;
408 }
409}};
410
411def template MiscExecute {{
412 Fault %(class_name)s::execute(ExecContext *xc,
413 Trace::InstRecord *traceData) const
414 {
415 Addr EA M5_VAR_USED = 0;
416 Fault fault = NoFault;
417
418 %(fp_enable_check)s;
419 %(op_decl)s;
420 %(op_rd)s;
421 %(ea_code)s;
422
423 if (fault == NoFault) {
424 %(memacc_code)s;
425 }
426
427 return NoFault;
428 }
429}};
430
431def template MiscInitiateAcc {{
432 Fault %(class_name)s::initiateAcc(ExecContext *xc,
433 Trace::InstRecord *traceData) const
434 {
435 panic("Misc instruction does not support split access method!");
436 return NoFault;
437 }
438}};
439
440
441def template MiscCompleteAcc {{
442 Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
443 Trace::InstRecord *traceData) const
444 {
445 panic("Misc instruction does not support split access method!");
446
447 return NoFault;
448 }
449}};
450
451def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
452 mem_flags = [], inst_flags = []) {{
453 (header_output, decoder_output, decode_block, exec_output) = \
454 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
455 decode_template = ImmNopCheckDecode,
456 exec_template_base = 'Load')
457}};
458
459
460def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
461 mem_flags = [], inst_flags = []) {{
462 (header_output, decoder_output, decode_block, exec_output) = \
463 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
464 exec_template_base = 'Store')
465}};
466
467def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
468 mem_flags = [], inst_flags = []) {{
469 inst_flags += ['IsIndexed']
470 (header_output, decoder_output, decode_block, exec_output) = \
471 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
472 decode_template = ImmNopCheckDecode,
473 exec_template_base = 'Load')
474}};
475
476def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
477 mem_flags = [], inst_flags = []) {{
478 inst_flags += ['IsIndexed']
479 (header_output, decoder_output, decode_block, exec_output) = \
480 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
481 exec_template_base = 'Store')
482}};
483
484def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
485 mem_flags = [], inst_flags = []) {{
486 inst_flags += ['IsIndexed', 'IsFloating']
487 (header_output, decoder_output, decode_block, exec_output) = \
488 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
489 decode_template = ImmNopCheckDecode,
490 exec_template_base = 'Load')
491}};
492
493def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
494 mem_flags = [], inst_flags = []) {{
495 inst_flags += ['IsIndexed', 'IsFloating']
496 (header_output, decoder_output, decode_block, exec_output) = \
497 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
498 exec_template_base = 'Store')
499}};
500
501
502def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
503 mem_flags = [], inst_flags = []) {{
504 decl_code = '''
505 uint32_t mem_word = Mem_uw;
506 uint32_t unalign_addr = Rs + disp;
507 uint32_t byte_offset = unalign_addr & 3;
508 if (GuestByteOrder == BigEndianByteOrder)
509 byte_offset ^= 3;
510 '''
511
512 memacc_code = decl_code + memacc_code
513
514 (header_output, decoder_output, decode_block, exec_output) = \
515 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
516 decode_template = ImmNopCheckDecode,
517 exec_template_base = 'Load')
518}};
519
520def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
521 mem_flags = [], inst_flags = []) {{
522 decl_code = '''
523 uint32_t mem_word = 0;
524 uint32_t unaligned_addr = Rs + disp;
525 uint32_t byte_offset = unaligned_addr & 3;
526 if (GuestByteOrder == BigEndianByteOrder)
527 byte_offset ^= 3;
528 fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags);
529 '''
530 memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
531
532 (header_output, decoder_output, decode_block, exec_output) = \
533 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
534 exec_template_base = 'Store')
535}};
536
537def format Prefetch(ea_code = {{ EA = Rs + disp; }},
538 mem_flags = [], pf_flags = [], inst_flags = []) {{
539 pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
540 pf_inst_flags = inst_flags
541
542 (header_output, decoder_output, decode_block, exec_output) = \
543 LoadStoreBase(name, Name, ea_code,
544 'warn_once("Prefetching not implemented for MIPS\\n");',
545 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
546
547}};
548
549def format StoreCond(memacc_code, postacc_code,
550 ea_code = {{ EA = Rs + disp; }},
551 mem_flags = [], inst_flags = []) {{
552 (header_output, decoder_output, decode_block, exec_output) = \
553 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
554 postacc_code, exec_template_base = 'StoreCond')
555}};
| 125 return 0;
126 }
127 }
128
129
130}};
131
132def template LoadStoreDeclare {{
133 /**
134 * Static instruction class for "%(mnemonic)s".
135 */
136 class %(class_name)s : public %(base_class)s
137 {
138 public:
139
140 /// Constructor.
141 %(class_name)s(ExtMachInst machInst);
142
143 Fault execute(ExecContext *, Trace::InstRecord *) const override;
144 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
145 Fault completeAcc(Packet *, ExecContext *,
146 Trace::InstRecord *) const override;
147 };
148}};
149
150
151def template LoadStoreConstructor {{
152 %(class_name)s::%(class_name)s(ExtMachInst machInst)
153 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
154 {
155 %(constructor)s;
156 }
157}};
158
159def template LoadExecute {{
160 Fault %(class_name)s::execute(ExecContext *xc,
161 Trace::InstRecord *traceData) const
162 {
163 Addr EA;
164 Fault fault = NoFault;
165
166 if (this->isFloating()) {
167 %(fp_enable_check)s;
168
169 if(fault != NoFault)
170 return fault;
171 }
172
173 %(op_decl)s;
174 %(op_rd)s;
175 %(ea_code)s;
176
177 if (fault == NoFault) {
178 fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
179 %(memacc_code)s;
180 }
181
182 if (fault == NoFault) {
183 %(op_wb)s;
184 }
185
186 return fault;
187 }
188}};
189
190
191def template LoadInitiateAcc {{
192 Fault %(class_name)s::initiateAcc(ExecContext *xc,
193 Trace::InstRecord *traceData) const
194 {
195 Addr EA;
196 Fault fault = NoFault;
197
198 if (this->isFloating()) {
199 %(fp_enable_check)s;
200
201 if(fault != NoFault)
202 return fault;
203 }
204
205 %(op_src_decl)s;
206 %(op_rd)s;
207 %(ea_code)s;
208
209 if (fault == NoFault) {
210 fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);
211 }
212
213 return fault;
214 }
215}};
216
217def template LoadCompleteAcc {{
218 Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
219 Trace::InstRecord *traceData) const
220 {
221 Fault fault = NoFault;
222
223 if (this->isFloating()) {
224 %(fp_enable_check)s;
225
226 if(fault != NoFault)
227 return fault;
228 }
229
230 %(op_decl)s;
231 %(op_rd)s;
232
233 getMem(pkt, Mem, traceData);
234
235 if (fault == NoFault) {
236 %(memacc_code)s;
237 }
238
239 if (fault == NoFault) {
240 %(op_wb)s;
241 }
242
243 return fault;
244 }
245}};
246
247def template StoreExecute {{
248 Fault %(class_name)s::execute(ExecContext *xc,
249 Trace::InstRecord *traceData) const
250 {
251 Addr EA;
252 Fault fault = NoFault;
253
254 %(fp_enable_check)s;
255 %(op_decl)s;
256 %(op_rd)s;
257 %(ea_code)s;
258
259 if (fault == NoFault) {
260 %(memacc_code)s;
261 }
262
263 if (fault == NoFault) {
264 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
265 NULL);
266 }
267
268 if (fault == NoFault) {
269 %(postacc_code)s;
270 }
271
272 if (fault == NoFault) {
273 %(op_wb)s;
274 }
275
276 return fault;
277 }
278}};
279
280
281def template StoreFPExecute {{
282 Fault %(class_name)s::execute(ExecContext *xc,
283 Trace::InstRecord *traceData) const
284 {
285 Addr EA;
286 Fault fault = NoFault;
287
288 %(fp_enable_check)s;
289 if(fault != NoFault)
290 return fault;
291 %(op_decl)s;
292 %(op_rd)s;
293 %(ea_code)s;
294
295 if (fault == NoFault) {
296 %(memacc_code)s;
297 }
298
299 if (fault == NoFault) {
300 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
301 NULL);
302 }
303
304 if (fault == NoFault) {
305 %(postacc_code)s;
306 }
307
308 if (fault == NoFault) {
309 %(op_wb)s;
310 }
311
312 return fault;
313 }
314}};
315
316def template StoreCondExecute {{
317 Fault %(class_name)s::execute(ExecContext *xc,
318 Trace::InstRecord *traceData) const
319 {
320 Addr EA;
321 Fault fault = NoFault;
322 uint64_t write_result = 0;
323
324 %(fp_enable_check)s;
325 %(op_decl)s;
326 %(op_rd)s;
327 %(ea_code)s;
328
329 if (fault == NoFault) {
330 %(memacc_code)s;
331 }
332
333 if (fault == NoFault) {
334 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
335 &write_result);
336 }
337
338 if (fault == NoFault) {
339 %(postacc_code)s;
340 }
341
342 if (fault == NoFault) {
343 %(op_wb)s;
344 }
345
346 return fault;
347 }
348}};
349
350def template StoreInitiateAcc {{
351 Fault %(class_name)s::initiateAcc(ExecContext *xc,
352 Trace::InstRecord *traceData) const
353 {
354 Addr EA;
355 Fault fault = NoFault;
356
357 %(fp_enable_check)s;
358 %(op_decl)s;
359 %(op_rd)s;
360 %(ea_code)s;
361
362 if (fault == NoFault) {
363 %(memacc_code)s;
364 }
365
366 if (fault == NoFault) {
367 fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
368 NULL);
369 }
370
371 return fault;
372 }
373}};
374
375
376def template StoreCompleteAcc {{
377 Fault %(class_name)s::completeAcc(Packet *pkt,
378 ExecContext *xc,
379 Trace::InstRecord *traceData) const
380 {
381 return NoFault;
382 }
383}};
384
385def template StoreCondCompleteAcc {{
386 Fault %(class_name)s::completeAcc(Packet *pkt,
387 ExecContext *xc,
388 Trace::InstRecord *traceData) const
389 {
390 Fault fault = NoFault;
391
392 %(fp_enable_check)s;
393 %(op_dest_decl)s;
394
395 uint64_t write_result = pkt->req->getExtraData();
396
397 if (fault == NoFault) {
398 %(postacc_code)s;
399 }
400
401 if (fault == NoFault) {
402 %(op_wb)s;
403 }
404
405 return fault;
406 }
407}};
408
409def template MiscExecute {{
410 Fault %(class_name)s::execute(ExecContext *xc,
411 Trace::InstRecord *traceData) const
412 {
413 Addr EA M5_VAR_USED = 0;
414 Fault fault = NoFault;
415
416 %(fp_enable_check)s;
417 %(op_decl)s;
418 %(op_rd)s;
419 %(ea_code)s;
420
421 if (fault == NoFault) {
422 %(memacc_code)s;
423 }
424
425 return NoFault;
426 }
427}};
428
429def template MiscInitiateAcc {{
430 Fault %(class_name)s::initiateAcc(ExecContext *xc,
431 Trace::InstRecord *traceData) const
432 {
433 panic("Misc instruction does not support split access method!");
434 return NoFault;
435 }
436}};
437
438
439def template MiscCompleteAcc {{
440 Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
441 Trace::InstRecord *traceData) const
442 {
443 panic("Misc instruction does not support split access method!");
444
445 return NoFault;
446 }
447}};
448
449def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
450 mem_flags = [], inst_flags = []) {{
451 (header_output, decoder_output, decode_block, exec_output) = \
452 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
453 decode_template = ImmNopCheckDecode,
454 exec_template_base = 'Load')
455}};
456
457
458def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
459 mem_flags = [], inst_flags = []) {{
460 (header_output, decoder_output, decode_block, exec_output) = \
461 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
462 exec_template_base = 'Store')
463}};
464
465def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
466 mem_flags = [], inst_flags = []) {{
467 inst_flags += ['IsIndexed']
468 (header_output, decoder_output, decode_block, exec_output) = \
469 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
470 decode_template = ImmNopCheckDecode,
471 exec_template_base = 'Load')
472}};
473
474def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
475 mem_flags = [], inst_flags = []) {{
476 inst_flags += ['IsIndexed']
477 (header_output, decoder_output, decode_block, exec_output) = \
478 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
479 exec_template_base = 'Store')
480}};
481
482def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
483 mem_flags = [], inst_flags = []) {{
484 inst_flags += ['IsIndexed', 'IsFloating']
485 (header_output, decoder_output, decode_block, exec_output) = \
486 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
487 decode_template = ImmNopCheckDecode,
488 exec_template_base = 'Load')
489}};
490
491def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
492 mem_flags = [], inst_flags = []) {{
493 inst_flags += ['IsIndexed', 'IsFloating']
494 (header_output, decoder_output, decode_block, exec_output) = \
495 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
496 exec_template_base = 'Store')
497}};
498
499
500def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
501 mem_flags = [], inst_flags = []) {{
502 decl_code = '''
503 uint32_t mem_word = Mem_uw;
504 uint32_t unalign_addr = Rs + disp;
505 uint32_t byte_offset = unalign_addr & 3;
506 if (GuestByteOrder == BigEndianByteOrder)
507 byte_offset ^= 3;
508 '''
509
510 memacc_code = decl_code + memacc_code
511
512 (header_output, decoder_output, decode_block, exec_output) = \
513 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
514 decode_template = ImmNopCheckDecode,
515 exec_template_base = 'Load')
516}};
517
518def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
519 mem_flags = [], inst_flags = []) {{
520 decl_code = '''
521 uint32_t mem_word = 0;
522 uint32_t unaligned_addr = Rs + disp;
523 uint32_t byte_offset = unaligned_addr & 3;
524 if (GuestByteOrder == BigEndianByteOrder)
525 byte_offset ^= 3;
526 fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags);
527 '''
528 memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
529
530 (header_output, decoder_output, decode_block, exec_output) = \
531 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
532 exec_template_base = 'Store')
533}};
534
535def format Prefetch(ea_code = {{ EA = Rs + disp; }},
536 mem_flags = [], pf_flags = [], inst_flags = []) {{
537 pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
538 pf_inst_flags = inst_flags
539
540 (header_output, decoder_output, decode_block, exec_output) = \
541 LoadStoreBase(name, Name, ea_code,
542 'warn_once("Prefetching not implemented for MIPS\\n");',
543 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
544
545}};
546
547def format StoreCond(memacc_code, postacc_code,
548 ea_code = {{ EA = Rs + disp; }},
549 mem_flags = [], inst_flags = []) {{
550 (header_output, decoder_output, decode_block, exec_output) = \
551 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
552 postacc_code, exec_template_base = 'StoreCond')
553}};
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