mem.isa (12236:126ac9da6050) mem.isa (12385:288c62455dde)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30// Korey Sewell
31
32////////////////////////////////////////////////////////////////////
33//
34// Memory-format instructions
35//
36
37output header {{
38 /**
39 * Base class for general Mips memory-format instructions.
40 */
41 class Memory : public MipsStaticInst
42 {
43 protected:
44 /// Memory request flags. See mem_req_base.hh.
45 Request::Flags memAccessFlags;
46
47 /// Displacement for EA calculation (signed).
48 int32_t disp;
49
50 /// Constructor
51 Memory(const char *mnem, MachInst _machInst, OpClass __opClass)
52 : MipsStaticInst(mnem, _machInst, __opClass),
53 disp(sext<16>(OFFSET))
54 {
55 }
56
57 std::string
58 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
59 };
60
61 /**
62 * Base class for a few miscellaneous memory-format insts
63 * that don't interpret the disp field
64 */
65 class MemoryNoDisp : public Memory
66 {
67 protected:
68 /// Constructor
69 MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
70 : Memory(mnem, _machInst, __opClass)
71 {
72 }
73
74 std::string
75 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
76 };
77}};
78
79
80output decoder {{
81 std::string
82 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
83 {
84 return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
85 flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
86 }
87
88 std::string
89 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
90 {
91 return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
92 flags[IsFloating] ? 'f' : 'r',
93 flags[IsFloating] ? FD : RD,
94 RS, RT);
95 }
96
97}};
98
99output header {{
100 uint64_t getMemData(ExecContext *xc, Packet *packet);
101
102}};
103
104output exec {{
105 /** return data in cases where there the size of data is only
106 known in the packet
107 */
108 uint64_t getMemData(ExecContext *xc, Packet *packet) {
109 switch (packet->getSize())
110 {
111 case 1:
112 return packet->get<uint8_t>();
113
114 case 2:
115 return packet->get<uint16_t>();
116
117 case 4:
118 return packet->get<uint32_t>();
119
120 case 8:
121 return packet->get<uint64_t>();
122
123 default:
124 std::cerr << "bad store data size = " << packet->getSize() << std::endl;
125
126 assert(0);
127 return 0;
128 }
129 }
130
131
132}};
133
134def template LoadStoreDeclare {{
135 /**
136 * Static instruction class for "%(mnemonic)s".
137 */
138 class %(class_name)s : public %(base_class)s
139 {
140 public:
141
142 /// Constructor.
143 %(class_name)s(ExtMachInst machInst);
144
145 Fault execute(ExecContext *, Trace::InstRecord *) const;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30// Korey Sewell
31
32////////////////////////////////////////////////////////////////////
33//
34// Memory-format instructions
35//
36
37output header {{
38 /**
39 * Base class for general Mips memory-format instructions.
40 */
41 class Memory : public MipsStaticInst
42 {
43 protected:
44 /// Memory request flags. See mem_req_base.hh.
45 Request::Flags memAccessFlags;
46
47 /// Displacement for EA calculation (signed).
48 int32_t disp;
49
50 /// Constructor
51 Memory(const char *mnem, MachInst _machInst, OpClass __opClass)
52 : MipsStaticInst(mnem, _machInst, __opClass),
53 disp(sext<16>(OFFSET))
54 {
55 }
56
57 std::string
58 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
59 };
60
61 /**
62 * Base class for a few miscellaneous memory-format insts
63 * that don't interpret the disp field
64 */
65 class MemoryNoDisp : public Memory
66 {
67 protected:
68 /// Constructor
69 MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
70 : Memory(mnem, _machInst, __opClass)
71 {
72 }
73
74 std::string
75 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
76 };
77}};
78
79
80output decoder {{
81 std::string
82 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
83 {
84 return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
85 flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
86 }
87
88 std::string
89 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
90 {
91 return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
92 flags[IsFloating] ? 'f' : 'r',
93 flags[IsFloating] ? FD : RD,
94 RS, RT);
95 }
96
97}};
98
99output header {{
100 uint64_t getMemData(ExecContext *xc, Packet *packet);
101
102}};
103
104output exec {{
105 /** return data in cases where there the size of data is only
106 known in the packet
107 */
108 uint64_t getMemData(ExecContext *xc, Packet *packet) {
109 switch (packet->getSize())
110 {
111 case 1:
112 return packet->get<uint8_t>();
113
114 case 2:
115 return packet->get<uint16_t>();
116
117 case 4:
118 return packet->get<uint32_t>();
119
120 case 8:
121 return packet->get<uint64_t>();
122
123 default:
124 std::cerr << "bad store data size = " << packet->getSize() << std::endl;
125
126 assert(0);
127 return 0;
128 }
129 }
130
131
132}};
133
134def template LoadStoreDeclare {{
135 /**
136 * Static instruction class for "%(mnemonic)s".
137 */
138 class %(class_name)s : public %(base_class)s
139 {
140 public:
141
142 /// Constructor.
143 %(class_name)s(ExtMachInst machInst);
144
145 Fault execute(ExecContext *, Trace::InstRecord *) const;
146 Fault eaComp(ExecContext *, Trace::InstRecord *) const;
147 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
148 Fault completeAcc(Packet *, ExecContext *, Trace::InstRecord *) const;
149 };
150}};
151
152
153def template LoadStoreConstructor {{
154 %(class_name)s::%(class_name)s(ExtMachInst machInst)
155 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
156 {
157 %(constructor)s;
158 }
159}};
160
146 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
147 Fault completeAcc(Packet *, ExecContext *, Trace::InstRecord *) const;
148 };
149}};
150
151
152def template LoadStoreConstructor {{
153 %(class_name)s::%(class_name)s(ExtMachInst machInst)
154 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
155 {
156 %(constructor)s;
157 }
158}};
159
161
162def template EACompExecute {{
163 Fault
164 %(class_name)s::eaComp(ExecContext *xc, Trace::InstRecord *traceData) const
165 {
166 Addr EA;
167 Fault fault = NoFault;
168
169 if (this->isFloating()) {
170 %(fp_enable_check)s;
171
172 if(fault != NoFault)
173 return fault;
174 }
175
176 %(op_decl)s;
177 %(op_rd)s;
178 %(ea_code)s;
179
180 // NOTE: Trace Data is written using execute or completeAcc templates
181 if (fault == NoFault) {
182 xc->setEA(EA);
183 }
184
185 return fault;
186 }
187}};
188
189def template LoadExecute {{
190 Fault %(class_name)s::execute(ExecContext *xc,
191 Trace::InstRecord *traceData) const
192 {
193 Addr EA;
194 Fault fault = NoFault;
195
196 if (this->isFloating()) {
197 %(fp_enable_check)s;
198
199 if(fault != NoFault)
200 return fault;
201 }
202
203 %(op_decl)s;
204 %(op_rd)s;
205 %(ea_code)s;
206
207 if (fault == NoFault) {
208 fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
209 %(memacc_code)s;
210 }
211
212 if (fault == NoFault) {
213 %(op_wb)s;
214 }
215
216 return fault;
217 }
218}};
219
220
221def template LoadInitiateAcc {{
222 Fault %(class_name)s::initiateAcc(ExecContext *xc,
223 Trace::InstRecord *traceData) const
224 {
225 Addr EA;
226 Fault fault = NoFault;
227
228 if (this->isFloating()) {
229 %(fp_enable_check)s;
230
231 if(fault != NoFault)
232 return fault;
233 }
234
235 %(op_src_decl)s;
236 %(op_rd)s;
237 %(ea_code)s;
238
239 if (fault == NoFault) {
240 fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);
241 }
242
243 return fault;
244 }
245}};
246
247def template LoadCompleteAcc {{
248 Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
249 Trace::InstRecord *traceData) const
250 {
251 Fault fault = NoFault;
252
253 if (this->isFloating()) {
254 %(fp_enable_check)s;
255
256 if(fault != NoFault)
257 return fault;
258 }
259
260 %(op_decl)s;
261 %(op_rd)s;
262
263 getMem(pkt, Mem, traceData);
264
265 if (fault == NoFault) {
266 %(memacc_code)s;
267 }
268
269 if (fault == NoFault) {
270 %(op_wb)s;
271 }
272
273 return fault;
274 }
275}};
276
277def template StoreExecute {{
278 Fault %(class_name)s::execute(ExecContext *xc,
279 Trace::InstRecord *traceData) const
280 {
281 Addr EA;
282 Fault fault = NoFault;
283
284 %(fp_enable_check)s;
285 %(op_decl)s;
286 %(op_rd)s;
287 %(ea_code)s;
288
289 if (fault == NoFault) {
290 %(memacc_code)s;
291 }
292
293 if (fault == NoFault) {
294 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
295 NULL);
296 }
297
298 if (fault == NoFault) {
299 %(postacc_code)s;
300 }
301
302 if (fault == NoFault) {
303 %(op_wb)s;
304 }
305
306 return fault;
307 }
308}};
309
310
311def template StoreFPExecute {{
312 Fault %(class_name)s::execute(ExecContext *xc,
313 Trace::InstRecord *traceData) const
314 {
315 Addr EA;
316 Fault fault = NoFault;
317
318 %(fp_enable_check)s;
319 if(fault != NoFault)
320 return fault;
321 %(op_decl)s;
322 %(op_rd)s;
323 %(ea_code)s;
324
325 if (fault == NoFault) {
326 %(memacc_code)s;
327 }
328
329 if (fault == NoFault) {
330 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
331 NULL);
332 }
333
334 if (fault == NoFault) {
335 %(postacc_code)s;
336 }
337
338 if (fault == NoFault) {
339 %(op_wb)s;
340 }
341
342 return fault;
343 }
344}};
345
346def template StoreCondExecute {{
347 Fault %(class_name)s::execute(ExecContext *xc,
348 Trace::InstRecord *traceData) const
349 {
350 Addr EA;
351 Fault fault = NoFault;
352 uint64_t write_result = 0;
353
354 %(fp_enable_check)s;
355 %(op_decl)s;
356 %(op_rd)s;
357 %(ea_code)s;
358
359 if (fault == NoFault) {
360 %(memacc_code)s;
361 }
362
363 if (fault == NoFault) {
364 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
365 &write_result);
366 }
367
368 if (fault == NoFault) {
369 %(postacc_code)s;
370 }
371
372 if (fault == NoFault) {
373 %(op_wb)s;
374 }
375
376 return fault;
377 }
378}};
379
380def template StoreInitiateAcc {{
381 Fault %(class_name)s::initiateAcc(ExecContext *xc,
382 Trace::InstRecord *traceData) const
383 {
384 Addr EA;
385 Fault fault = NoFault;
386
387 %(fp_enable_check)s;
388 %(op_decl)s;
389 %(op_rd)s;
390 %(ea_code)s;
391
392 if (fault == NoFault) {
393 %(memacc_code)s;
394 }
395
396 if (fault == NoFault) {
397 fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
398 NULL);
399 }
400
401 return fault;
402 }
403}};
404
405
406def template StoreCompleteAcc {{
407 Fault %(class_name)s::completeAcc(Packet *pkt,
408 ExecContext *xc,
409 Trace::InstRecord *traceData) const
410 {
411 return NoFault;
412 }
413}};
414
415def template StoreCondCompleteAcc {{
416 Fault %(class_name)s::completeAcc(Packet *pkt,
417 ExecContext *xc,
418 Trace::InstRecord *traceData) const
419 {
420 Fault fault = NoFault;
421
422 %(fp_enable_check)s;
423 %(op_dest_decl)s;
424
425 uint64_t write_result = pkt->req->getExtraData();
426
427 if (fault == NoFault) {
428 %(postacc_code)s;
429 }
430
431 if (fault == NoFault) {
432 %(op_wb)s;
433 }
434
435 return fault;
436 }
437}};
438
439def template MiscExecute {{
440 Fault %(class_name)s::execute(ExecContext *xc,
441 Trace::InstRecord *traceData) const
442 {
443 Addr EA M5_VAR_USED = 0;
444 Fault fault = NoFault;
445
446 %(fp_enable_check)s;
447 %(op_decl)s;
448 %(op_rd)s;
449 %(ea_code)s;
450
451 if (fault == NoFault) {
452 %(memacc_code)s;
453 }
454
455 return NoFault;
456 }
457}};
458
459def template MiscInitiateAcc {{
460 Fault %(class_name)s::initiateAcc(ExecContext *xc,
461 Trace::InstRecord *traceData) const
462 {
463 panic("Misc instruction does not support split access method!");
464 return NoFault;
465 }
466}};
467
468
469def template MiscCompleteAcc {{
470 Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
471 Trace::InstRecord *traceData) const
472 {
473 panic("Misc instruction does not support split access method!");
474
475 return NoFault;
476 }
477}};
478
479def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
480 mem_flags = [], inst_flags = []) {{
481 (header_output, decoder_output, decode_block, exec_output) = \
482 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
483 decode_template = ImmNopCheckDecode,
484 exec_template_base = 'Load')
485}};
486
487
488def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
489 mem_flags = [], inst_flags = []) {{
490 (header_output, decoder_output, decode_block, exec_output) = \
491 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
492 exec_template_base = 'Store')
493}};
494
495def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
496 mem_flags = [], inst_flags = []) {{
497 inst_flags += ['IsIndexed']
498 (header_output, decoder_output, decode_block, exec_output) = \
499 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
500 decode_template = ImmNopCheckDecode,
501 exec_template_base = 'Load')
502}};
503
504def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
505 mem_flags = [], inst_flags = []) {{
506 inst_flags += ['IsIndexed']
507 (header_output, decoder_output, decode_block, exec_output) = \
508 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
509 exec_template_base = 'Store')
510}};
511
512def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
513 mem_flags = [], inst_flags = []) {{
514 inst_flags += ['IsIndexed', 'IsFloating']
515 (header_output, decoder_output, decode_block, exec_output) = \
516 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
517 decode_template = ImmNopCheckDecode,
518 exec_template_base = 'Load')
519}};
520
521def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
522 mem_flags = [], inst_flags = []) {{
523 inst_flags += ['IsIndexed', 'IsFloating']
524 (header_output, decoder_output, decode_block, exec_output) = \
525 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
526 exec_template_base = 'Store')
527}};
528
529
530def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
531 mem_flags = [], inst_flags = []) {{
532 decl_code = '''
533 uint32_t mem_word = Mem_uw;
534 uint32_t unalign_addr = Rs + disp;
535 uint32_t byte_offset = unalign_addr & 3;
536 if (GuestByteOrder == BigEndianByteOrder)
537 byte_offset ^= 3;
538 '''
539
540 memacc_code = decl_code + memacc_code
541
542 (header_output, decoder_output, decode_block, exec_output) = \
543 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
544 decode_template = ImmNopCheckDecode,
545 exec_template_base = 'Load')
546}};
547
548def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
549 mem_flags = [], inst_flags = []) {{
550 decl_code = '''
551 uint32_t mem_word = 0;
552 uint32_t unaligned_addr = Rs + disp;
553 uint32_t byte_offset = unaligned_addr & 3;
554 if (GuestByteOrder == BigEndianByteOrder)
555 byte_offset ^= 3;
556 fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags);
557 '''
558 memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
559
560 (header_output, decoder_output, decode_block, exec_output) = \
561 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
562 exec_template_base = 'Store')
563}};
564
565def format Prefetch(ea_code = {{ EA = Rs + disp; }},
566 mem_flags = [], pf_flags = [], inst_flags = []) {{
567 pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
568 pf_inst_flags = inst_flags
569
570 (header_output, decoder_output, decode_block, exec_output) = \
571 LoadStoreBase(name, Name, ea_code,
572 'warn_once("Prefetching not implemented for MIPS\\n");',
573 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
574
575}};
576
577def format StoreCond(memacc_code, postacc_code,
578 ea_code = {{ EA = Rs + disp; }},
579 mem_flags = [], inst_flags = []) {{
580 (header_output, decoder_output, decode_block, exec_output) = \
581 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
582 postacc_code, exec_template_base = 'StoreCond')
583}};
160def template LoadExecute {{
161 Fault %(class_name)s::execute(ExecContext *xc,
162 Trace::InstRecord *traceData) const
163 {
164 Addr EA;
165 Fault fault = NoFault;
166
167 if (this->isFloating()) {
168 %(fp_enable_check)s;
169
170 if(fault != NoFault)
171 return fault;
172 }
173
174 %(op_decl)s;
175 %(op_rd)s;
176 %(ea_code)s;
177
178 if (fault == NoFault) {
179 fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
180 %(memacc_code)s;
181 }
182
183 if (fault == NoFault) {
184 %(op_wb)s;
185 }
186
187 return fault;
188 }
189}};
190
191
192def template LoadInitiateAcc {{
193 Fault %(class_name)s::initiateAcc(ExecContext *xc,
194 Trace::InstRecord *traceData) const
195 {
196 Addr EA;
197 Fault fault = NoFault;
198
199 if (this->isFloating()) {
200 %(fp_enable_check)s;
201
202 if(fault != NoFault)
203 return fault;
204 }
205
206 %(op_src_decl)s;
207 %(op_rd)s;
208 %(ea_code)s;
209
210 if (fault == NoFault) {
211 fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);
212 }
213
214 return fault;
215 }
216}};
217
218def template LoadCompleteAcc {{
219 Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
220 Trace::InstRecord *traceData) const
221 {
222 Fault fault = NoFault;
223
224 if (this->isFloating()) {
225 %(fp_enable_check)s;
226
227 if(fault != NoFault)
228 return fault;
229 }
230
231 %(op_decl)s;
232 %(op_rd)s;
233
234 getMem(pkt, Mem, traceData);
235
236 if (fault == NoFault) {
237 %(memacc_code)s;
238 }
239
240 if (fault == NoFault) {
241 %(op_wb)s;
242 }
243
244 return fault;
245 }
246}};
247
248def template StoreExecute {{
249 Fault %(class_name)s::execute(ExecContext *xc,
250 Trace::InstRecord *traceData) const
251 {
252 Addr EA;
253 Fault fault = NoFault;
254
255 %(fp_enable_check)s;
256 %(op_decl)s;
257 %(op_rd)s;
258 %(ea_code)s;
259
260 if (fault == NoFault) {
261 %(memacc_code)s;
262 }
263
264 if (fault == NoFault) {
265 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
266 NULL);
267 }
268
269 if (fault == NoFault) {
270 %(postacc_code)s;
271 }
272
273 if (fault == NoFault) {
274 %(op_wb)s;
275 }
276
277 return fault;
278 }
279}};
280
281
282def template StoreFPExecute {{
283 Fault %(class_name)s::execute(ExecContext *xc,
284 Trace::InstRecord *traceData) const
285 {
286 Addr EA;
287 Fault fault = NoFault;
288
289 %(fp_enable_check)s;
290 if(fault != NoFault)
291 return fault;
292 %(op_decl)s;
293 %(op_rd)s;
294 %(ea_code)s;
295
296 if (fault == NoFault) {
297 %(memacc_code)s;
298 }
299
300 if (fault == NoFault) {
301 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
302 NULL);
303 }
304
305 if (fault == NoFault) {
306 %(postacc_code)s;
307 }
308
309 if (fault == NoFault) {
310 %(op_wb)s;
311 }
312
313 return fault;
314 }
315}};
316
317def template StoreCondExecute {{
318 Fault %(class_name)s::execute(ExecContext *xc,
319 Trace::InstRecord *traceData) const
320 {
321 Addr EA;
322 Fault fault = NoFault;
323 uint64_t write_result = 0;
324
325 %(fp_enable_check)s;
326 %(op_decl)s;
327 %(op_rd)s;
328 %(ea_code)s;
329
330 if (fault == NoFault) {
331 %(memacc_code)s;
332 }
333
334 if (fault == NoFault) {
335 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
336 &write_result);
337 }
338
339 if (fault == NoFault) {
340 %(postacc_code)s;
341 }
342
343 if (fault == NoFault) {
344 %(op_wb)s;
345 }
346
347 return fault;
348 }
349}};
350
351def template StoreInitiateAcc {{
352 Fault %(class_name)s::initiateAcc(ExecContext *xc,
353 Trace::InstRecord *traceData) const
354 {
355 Addr EA;
356 Fault fault = NoFault;
357
358 %(fp_enable_check)s;
359 %(op_decl)s;
360 %(op_rd)s;
361 %(ea_code)s;
362
363 if (fault == NoFault) {
364 %(memacc_code)s;
365 }
366
367 if (fault == NoFault) {
368 fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
369 NULL);
370 }
371
372 return fault;
373 }
374}};
375
376
377def template StoreCompleteAcc {{
378 Fault %(class_name)s::completeAcc(Packet *pkt,
379 ExecContext *xc,
380 Trace::InstRecord *traceData) const
381 {
382 return NoFault;
383 }
384}};
385
386def template StoreCondCompleteAcc {{
387 Fault %(class_name)s::completeAcc(Packet *pkt,
388 ExecContext *xc,
389 Trace::InstRecord *traceData) const
390 {
391 Fault fault = NoFault;
392
393 %(fp_enable_check)s;
394 %(op_dest_decl)s;
395
396 uint64_t write_result = pkt->req->getExtraData();
397
398 if (fault == NoFault) {
399 %(postacc_code)s;
400 }
401
402 if (fault == NoFault) {
403 %(op_wb)s;
404 }
405
406 return fault;
407 }
408}};
409
410def template MiscExecute {{
411 Fault %(class_name)s::execute(ExecContext *xc,
412 Trace::InstRecord *traceData) const
413 {
414 Addr EA M5_VAR_USED = 0;
415 Fault fault = NoFault;
416
417 %(fp_enable_check)s;
418 %(op_decl)s;
419 %(op_rd)s;
420 %(ea_code)s;
421
422 if (fault == NoFault) {
423 %(memacc_code)s;
424 }
425
426 return NoFault;
427 }
428}};
429
430def template MiscInitiateAcc {{
431 Fault %(class_name)s::initiateAcc(ExecContext *xc,
432 Trace::InstRecord *traceData) const
433 {
434 panic("Misc instruction does not support split access method!");
435 return NoFault;
436 }
437}};
438
439
440def template MiscCompleteAcc {{
441 Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
442 Trace::InstRecord *traceData) const
443 {
444 panic("Misc instruction does not support split access method!");
445
446 return NoFault;
447 }
448}};
449
450def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
451 mem_flags = [], inst_flags = []) {{
452 (header_output, decoder_output, decode_block, exec_output) = \
453 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
454 decode_template = ImmNopCheckDecode,
455 exec_template_base = 'Load')
456}};
457
458
459def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
460 mem_flags = [], inst_flags = []) {{
461 (header_output, decoder_output, decode_block, exec_output) = \
462 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
463 exec_template_base = 'Store')
464}};
465
466def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
467 mem_flags = [], inst_flags = []) {{
468 inst_flags += ['IsIndexed']
469 (header_output, decoder_output, decode_block, exec_output) = \
470 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
471 decode_template = ImmNopCheckDecode,
472 exec_template_base = 'Load')
473}};
474
475def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
476 mem_flags = [], inst_flags = []) {{
477 inst_flags += ['IsIndexed']
478 (header_output, decoder_output, decode_block, exec_output) = \
479 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
480 exec_template_base = 'Store')
481}};
482
483def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
484 mem_flags = [], inst_flags = []) {{
485 inst_flags += ['IsIndexed', 'IsFloating']
486 (header_output, decoder_output, decode_block, exec_output) = \
487 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
488 decode_template = ImmNopCheckDecode,
489 exec_template_base = 'Load')
490}};
491
492def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
493 mem_flags = [], inst_flags = []) {{
494 inst_flags += ['IsIndexed', 'IsFloating']
495 (header_output, decoder_output, decode_block, exec_output) = \
496 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
497 exec_template_base = 'Store')
498}};
499
500
501def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
502 mem_flags = [], inst_flags = []) {{
503 decl_code = '''
504 uint32_t mem_word = Mem_uw;
505 uint32_t unalign_addr = Rs + disp;
506 uint32_t byte_offset = unalign_addr & 3;
507 if (GuestByteOrder == BigEndianByteOrder)
508 byte_offset ^= 3;
509 '''
510
511 memacc_code = decl_code + memacc_code
512
513 (header_output, decoder_output, decode_block, exec_output) = \
514 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
515 decode_template = ImmNopCheckDecode,
516 exec_template_base = 'Load')
517}};
518
519def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
520 mem_flags = [], inst_flags = []) {{
521 decl_code = '''
522 uint32_t mem_word = 0;
523 uint32_t unaligned_addr = Rs + disp;
524 uint32_t byte_offset = unaligned_addr & 3;
525 if (GuestByteOrder == BigEndianByteOrder)
526 byte_offset ^= 3;
527 fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags);
528 '''
529 memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
530
531 (header_output, decoder_output, decode_block, exec_output) = \
532 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
533 exec_template_base = 'Store')
534}};
535
536def format Prefetch(ea_code = {{ EA = Rs + disp; }},
537 mem_flags = [], pf_flags = [], inst_flags = []) {{
538 pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
539 pf_inst_flags = inst_flags
540
541 (header_output, decoder_output, decode_block, exec_output) = \
542 LoadStoreBase(name, Name, ea_code,
543 'warn_once("Prefetching not implemented for MIPS\\n");',
544 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
545
546}};
547
548def format StoreCond(memacc_code, postacc_code,
549 ea_code = {{ EA = Rs + disp; }},
550 mem_flags = [], inst_flags = []) {{
551 (header_output, decoder_output, decode_block, exec_output) = \
552 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
553 postacc_code, exec_template_base = 'StoreCond')
554}};