1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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64
65 std::string
66 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
67
68 public:
69
70 const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
71 const StaticInstPtr &memAccInst() const { return memAccPtr; }
72 };
73
74 /**
75 * Base class for a few miscellaneous memory-format insts
76 * that don't interpret the disp field
77 */
78 class MemoryNoDisp : public Memory
79 {

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103 std::string
104 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
105 {
106 return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
107 flags[IsFloating] ? 'f' : 'r',
108 flags[IsFloating] ? FD : RD,
109 RS, RT);
110 }
111}};
112
113def template LoadStoreDeclare {{
114 /**
115 * Static instruction class for "%(mnemonic)s".
116 */
117 class %(class_name)s : public %(base_class)s
118 {
119 protected:
120
121 /**
122 * "Fake" effective address computation class for "%(mnemonic)s".
123 */
124 class EAComp : public %(base_class)s
125 {
126 public:
127 /// Constructor
128 EAComp(MachInst machInst);
129
130 %(BasicExecDeclare)s
131 };
132
133 /**
134 * "Fake" memory access instruction class for "%(mnemonic)s".
135 */
136 class MemAcc : public %(base_class)s
137 {
138 public:
139 /// Constructor
140 MemAcc(MachInst machInst);
141
142 %(BasicExecDeclare)s
143 };
144
145 public:
146
147 /// Constructor.
148 %(class_name)s(MachInst machInst);
149
150 %(BasicExecDeclare)s
151
152 %(InitiateAccDeclare)s
153
154 %(CompleteAccDeclare)s
155 };
156}};
157
158
159def template InitiateAccDeclare {{
160 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
161}};
162
163
164def template CompleteAccDeclare {{
165 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
166}};
167
168
169def template EACompConstructor {{
170 /** TODO: change op_class to AddrGenOp or something (requires
171 * creating new member of OpClass enum in op_class.hh, updating
172 * config files, etc.). */
173 inline %(class_name)s::EAComp::EAComp(MachInst machInst)
174 : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
175 {
176 %(constructor)s;
177 }
178}};
179
180
181def template MemAccConstructor {{
182 inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
183 : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
184 {
185 %(constructor)s;
186 }
187}};
188
189
190def template LoadStoreConstructor {{
191 inline %(class_name)s::%(class_name)s(MachInst machInst)
192 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
193 new EAComp(machInst), new MemAcc(machInst))
194 {
195 %(constructor)s;
196 }
197}};
198
199

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205 Addr EA;
206 Fault fault = NoFault;
207
208 %(fp_enable_check)s;
209 %(op_decl)s;
210 %(op_rd)s;
211 %(ea_code)s;
212
213 if (fault == NoFault) {
214 %(op_wb)s;
215 xc->setEA(EA);
216 }
217
218 return fault;
219 }
220}};
221
222def template LoadMemAccExecute {{
223 Fault
224 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
225 Trace::InstRecord *traceData) const
226 {
227 Addr EA;
228 Fault fault = NoFault;
229
230 %(fp_enable_check)s;
231 %(op_decl)s;
232 %(op_rd)s;
233 EA = xc->getEA();
234
235 if (fault == NoFault) {
236 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
237 %(memacc_code)s;
238 }
239
240 if (fault == NoFault) {
241 %(op_wb)s;
242 }
243
244 return fault;
245 }
246}};
247
248
249def template LoadExecute {{
250 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
251 Trace::InstRecord *traceData) const

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287 if (fault == NoFault) {
288 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
289 }
290
291 return fault;
292 }
293}};
294
295
296def template LoadCompleteAcc {{
297 Fault %(class_name)s::completeAcc(PacketPtr pkt,
298 %(CPU_exec_context)s *xc,
299 Trace::InstRecord *traceData) const
300 {
301 Fault fault = NoFault;
302
303 %(fp_enable_check)s;
304 %(op_decl)s;
305
306 Mem = pkt->get<typeof(Mem)>();
307
308 if (fault == NoFault) {
309 %(memacc_code)s;
310 }
311
312 if (fault == NoFault) {
313 %(op_wb)s;
314 }
315
316 return fault;
317 }
318}};
319
320
321def template StoreMemAccExecute {{
322 Fault
323 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
324 Trace::InstRecord *traceData) const
325 {
326 Addr EA;
327 Fault fault = NoFault;
328
329 %(fp_enable_check)s;
330 %(op_decl)s;
331 %(op_rd)s;
332 EA = xc->getEA();
333
334 if (fault == NoFault) {
335 %(memacc_code)s;
336 }
337
338 if (fault == NoFault) {
339 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
340 memAccessFlags, NULL);
341 if (traceData) { traceData->setData(Mem); }
342 }
343
344 if (fault == NoFault) {
345 %(postacc_code)s;
346 }
347
348 if (fault == NoFault) {
349 %(op_wb)s;
350 }
351
352 return fault;
353 }
354}};
355
356def template StoreCondMemAccExecute {{
357 Fault
358 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
359 Trace::InstRecord *traceData) const

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384 if (fault == NoFault) {
385 %(op_wb)s;
386 }
387
388 return fault;
389 }
390}};
391
392
393def template StoreExecute {{
394 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
395 Trace::InstRecord *traceData) const
396 {
397 Addr EA;
398 Fault fault = NoFault;
399
400 %(fp_enable_check)s;
401 %(op_decl)s;
402 %(op_rd)s;
403 %(ea_code)s;
404
405 if (fault == NoFault) {
406 %(memacc_code)s;
407 }
408
409 if (fault == NoFault) {
410 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
411 memAccessFlags, NULL);
412 if (traceData) { traceData->setData(Mem); }
413 }
414
415 if (fault == NoFault) {
416 %(postacc_code)s;
417 }
418
419 if (fault == NoFault) {

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482 }
483
484 return fault;
485 }
486}};
487
488
489def template StoreCompleteAcc {{
490 Fault %(class_name)s::completeAcc(PacketPtr pkt,
491 %(CPU_exec_context)s *xc,
492 Trace::InstRecord *traceData) const
493 {
494 Fault fault = NoFault;
495
496 %(fp_enable_check)s;
497 %(op_dest_decl)s;
498
499 if (fault == NoFault) {
500 %(postacc_code)s;
501 }
502
503 if (fault == NoFault) {
504 %(op_wb)s;
505 }
506
507 return fault;
508 }
509}};
510
511def template StoreCondCompleteAcc {{
512 Fault %(class_name)s::completeAcc(PacketPtr pkt,
513 %(CPU_exec_context)s *xc,
514 Trace::InstRecord *traceData) const
515 {
516 Fault fault = NoFault;
517
518 %(fp_enable_check)s;
519 %(op_dest_decl)s;
520

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579 {
580 panic("Misc instruction does not support split access method!");
581 return NoFault;
582 }
583}};
584
585
586def template MiscCompleteAcc {{
587 Fault %(class_name)s::completeAcc(PacketPtr pkt,
588 %(CPU_exec_context)s *xc,
589 Trace::InstRecord *traceData) const
590 {
591 panic("Misc instruction does not support split access method!");
592
593 return NoFault;
594 }
595}};
596
597def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
598 mem_flags = [], inst_flags = []) {{
599 (header_output, decoder_output, decode_block, exec_output) = \
600 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
601 decode_template = ImmNopCheckDecode,
602 exec_template_base = 'Load')
603}};
604

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645 mem_flags = [], inst_flags = []) {{
646 decl_code = 'uint32_t mem_word = 0;\n'
647 decl_code += 'uint32_t unaligned_addr = Rs + disp;\n'
648 decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n'
649 decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
650 decl_code += '\tbyte_offset ^= 3;\n'
651 decl_code += '#endif\n'
652 decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n'
653 memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
654
655 (header_output, decoder_output, decode_block, exec_output) = \
656 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
657 exec_template_base = 'Store')
658}};
659
660def format Prefetch(ea_code = {{ EA = Rs + disp; }},

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