1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Gabe Black
30// Korey Sewell
31
32////////////////////////////////////////////////////////////////////
33//
34// Memory-format instructions
35//
36
37output header {{

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157
158
159def template InitiateAccDeclare {{
160 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
161}};
162
163
164def template CompleteAccDeclare {{
165 Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
166}};
167
168
169def template LoadStoreConstructor {{
170 /** TODO: change op_class to AddrGenOp or something (requires
171 * creating new member of OpClass enum in op_class.hh, updating
172 * config files, etc.). */
173 inline %(class_name)s::EAComp::EAComp(MachInst machInst)

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283 }
284
285 return fault;
286 }
287}};
288
289
290def template LoadCompleteAcc {{
291 Fault %(class_name)s::completeAcc(uint8_t *data,
292 %(CPU_exec_context)s *xc,
293 Trace::InstRecord *traceData) const
294 {
295 Fault fault = NoFault;
296
297 %(fp_enable_check)s;
298 %(op_decl)s;
299
300 memcpy(&Mem, data, sizeof(Mem));
301
302 if (fault == NoFault) {
303 %(memacc_code)s;
304 }
305
306 if (fault == NoFault) {
307 %(op_wb)s;
308 }

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385}};
386
387def template StoreInitiateAcc {{
388 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
389 Trace::InstRecord *traceData) const
390 {
391 Addr EA;
392 Fault fault = NoFault;
393 uint64_t write_result = 0;
394
395 %(fp_enable_check)s;
396 %(op_decl)s;
397 %(op_rd)s;
398 %(ea_code)s;
399
400 if (fault == NoFault) {
401 %(memacc_code)s;
402 }
403
404 if (fault == NoFault) {
405 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
406 memAccessFlags, &write_result);
407 if (traceData) { traceData->setData(Mem); }
408 }
409
410 return fault;
411 }
412}};
413
414
415def template StoreCompleteAcc {{
416 Fault %(class_name)s::completeAcc(uint8_t *data,
417 %(CPU_exec_context)s *xc,
418 Trace::InstRecord *traceData) const
419 {
420 Fault fault = NoFault;
421 uint64_t write_result = 0;
422
423 %(fp_enable_check)s;
424 %(op_dest_decl)s;
425
426 memcpy(&write_result, data, sizeof(write_result));
427
428 if (fault == NoFault) {
429 %(postacc_code)s;
430 }
431
432 if (fault == NoFault) {
433 %(op_wb)s;
434 }
435
436 return fault;

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484 {
485 panic("Misc instruction does not support split access method!");
486 return NoFault;
487 }
488}};
489
490
491def template MiscCompleteAcc {{
492 Fault %(class_name)s::completeAcc(uint8_t *data,
493 %(CPU_exec_context)s *xc,
494 Trace::InstRecord *traceData) const
495 {
496 panic("Misc instruction does not support split access method!");
497
498 return NoFault;
499 }
500}};

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575
576}};
577
578def format StoreCond(memacc_code, postacc_code,
579 ea_code = {{ EA = Rs + disp; }},
580 mem_flags = [], inst_flags = []) {{
581 (header_output, decoder_output, decode_block, exec_output) = \
582 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
583 postacc_code, exec_template_base = 'Store')
584}};