1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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92 flags[IsFloating] ? 'f' : 'r',
93 flags[IsFloating] ? FD : RD,
94 RS, RT);
95 }
96
97}};
98
99output header {{
100 uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet);
101
102}};
103
104output exec {{
105 /** return data in cases where there the size of data is only
106 known in the packet
107 */
108 uint64_t getMemData(CPU_EXEC_CONTEXT *xc, Packet *packet) {
109 switch (packet->getSize())
110 {
111 case 1:
112 return packet->get<uint8_t>();
113
114 case 2:
115 return packet->get<uint16_t>();
116

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148
149 %(InitiateAccDeclare)s
150
151 %(CompleteAccDeclare)s
152 };
153}};
154
155def template EACompDeclare {{
156 Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
157}};
158
159def template InitiateAccDeclare {{
160 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
161}};
162
163
164def template CompleteAccDeclare {{
165 Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
166}};
167
168def template LoadStoreConstructor {{
169 %(class_name)s::%(class_name)s(ExtMachInst machInst)
170 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
171 {
172 %(constructor)s;
173 }
174}};
175
176
177def template EACompExecute {{
178 Fault
179 %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
180 Trace::InstRecord *traceData) const
181 {
182 Addr EA;
183 Fault fault = NoFault;
184
185 if (this->isFloating()) {
186 %(fp_enable_check)s;
187
188 if(fault != NoFault)

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198 xc->setEA(EA);
199 }
200
201 return fault;
202 }
203}};
204
205def template LoadExecute {{
206 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
207 Trace::InstRecord *traceData) const
208 {
209 Addr EA;
210 Fault fault = NoFault;
211
212 if (this->isFloating()) {
213 %(fp_enable_check)s;
214

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230 }
231
232 return fault;
233 }
234}};
235
236
237def template LoadInitiateAcc {{
238 Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
239 Trace::InstRecord *traceData) const
240 {
241 Addr EA;
242 Fault fault = NoFault;
243
244 if (this->isFloating()) {
245 %(fp_enable_check)s;
246

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256 fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);
257 }
258
259 return fault;
260 }
261}};
262
263def template LoadCompleteAcc {{
264 Fault %(class_name)s::completeAcc(Packet *pkt,
265 CPU_EXEC_CONTEXT *xc,
266 Trace::InstRecord *traceData) const
267 {
268 Fault fault = NoFault;
269
270 if (this->isFloating()) {
271 %(fp_enable_check)s;
272
273 if(fault != NoFault)

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287 %(op_wb)s;
288 }
289
290 return fault;
291 }
292}};
293
294def template StoreExecute {{
295 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
296 Trace::InstRecord *traceData) const
297 {
298 Addr EA;
299 Fault fault = NoFault;
300
301 %(fp_enable_check)s;
302 %(op_decl)s;
303 %(op_rd)s;

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321 }
322
323 return fault;
324 }
325}};
326
327
328def template StoreFPExecute {{
329 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
330 Trace::InstRecord *traceData) const
331 {
332 Addr EA;
333 Fault fault = NoFault;
334
335 %(fp_enable_check)s;
336 if(fault != NoFault)
337 return fault;

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356 %(op_wb)s;
357 }
358
359 return fault;
360 }
361}};
362
363def template StoreCondExecute {{
364 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
365 Trace::InstRecord *traceData) const
366 {
367 Addr EA;
368 Fault fault = NoFault;
369 uint64_t write_result = 0;
370
371 %(fp_enable_check)s;
372 %(op_decl)s;

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390 %(op_wb)s;
391 }
392
393 return fault;
394 }
395}};
396
397def template StoreInitiateAcc {{
398 Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
399 Trace::InstRecord *traceData) const
400 {
401 Addr EA;
402 Fault fault = NoFault;
403
404 %(fp_enable_check)s;
405 %(op_decl)s;
406 %(op_rd)s;

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417
418 return fault;
419 }
420}};
421
422
423def template StoreCompleteAcc {{
424 Fault %(class_name)s::completeAcc(Packet *pkt,
425 CPU_EXEC_CONTEXT *xc,
426 Trace::InstRecord *traceData) const
427 {
428 return NoFault;
429 }
430}};
431
432def template StoreCondCompleteAcc {{
433 Fault %(class_name)s::completeAcc(Packet *pkt,
434 CPU_EXEC_CONTEXT *xc,
435 Trace::InstRecord *traceData) const
436 {
437 Fault fault = NoFault;
438
439 %(fp_enable_check)s;
440 %(op_dest_decl)s;
441
442 uint64_t write_result = pkt->req->getExtraData();

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449 %(op_wb)s;
450 }
451
452 return fault;
453 }
454}};
455
456def template MiscExecute {{
457 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
458 Trace::InstRecord *traceData) const
459 {
460 Addr EA M5_VAR_USED = 0;
461 Fault fault = NoFault;
462
463 %(fp_enable_check)s;
464 %(op_decl)s;
465 %(op_rd)s;
466 %(ea_code)s;
467
468 if (fault == NoFault) {
469 %(memacc_code)s;
470 }
471
472 return NoFault;
473 }
474}};
475
476def template MiscInitiateAcc {{
477 Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
478 Trace::InstRecord *traceData) const
479 {
480 panic("Misc instruction does not support split access method!");
481 return NoFault;
482 }
483}};
484
485
486def template MiscCompleteAcc {{
487 Fault %(class_name)s::completeAcc(Packet *pkt,
488 CPU_EXEC_CONTEXT *xc,
489 Trace::InstRecord *traceData) const
490 {
491 panic("Misc instruction does not support split access method!");
492
493 return NoFault;
494 }
495}};
496

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