1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 528 unchanged lines hidden (view full) ---

537 (header_output, decoder_output, decode_block, exec_output) = \
538 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
539 exec_template_base = 'Store')
540}};
541
542
543def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
544 mem_flags = [], inst_flags = []) {{
545 decl_code = '''
546 uint32_t mem_word = Mem.uw;
547 uint32_t unalign_addr = Rs + disp;
548 uint32_t byte_offset = unalign_addr & 3;
549 if (GuestByteOrder == BigEndianByteOrder)
550 byte_offset ^= 3;
551 '''
552
553 memacc_code = decl_code + memacc_code
554
555 (header_output, decoder_output, decode_block, exec_output) = \
556 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
557 decode_template = ImmNopCheckDecode,
558 exec_template_base = 'Load')
559}};
560
561def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
562 mem_flags = [], inst_flags = []) {{
563 decl_code = '''
564 uint32_t mem_word = 0;
565 uint32_t unaligned_addr = Rs + disp;
566 uint32_t byte_offset = unaligned_addr & 3;
567 if (GuestByteOrder == BigEndianByteOrder)
568 byte_offset ^= 3;
569 fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags);
570 '''
571 memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
572
573 (header_output, decoder_output, decode_block, exec_output) = \
574 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
575 exec_template_base = 'Store')
576}};

--- 20 unchanged lines hidden ---