1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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494 Trace::InstRecord *traceData) const
495 {
496 panic("Misc instruction does not support split access method!");
497
498 return NoFault;
499 }
500}};
501
502def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
503 mem_flags = [], inst_flags = []) {{
504 (header_output, decoder_output, decode_block, exec_output) = \
505 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
506 decode_template = ImmNopCheckDecode,
507 exec_template_base = 'Load')
508}};
509
510def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
511 mem_flags = [], inst_flags = []) {{
512 (header_output, decoder_output, decode_block, exec_output) = \
513 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
514 exec_template_base = 'Store')
515}};
516
517def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
518 mem_flags = [], inst_flags = []) {{
519 (header_output, decoder_output, decode_block, exec_output) = \
520 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
521 decode_template = ImmNopCheckDecode,
522 exec_template_base = 'Load')
523}};
524
525def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
526 mem_flags = [], inst_flags = []) {{
527 (header_output, decoder_output, decode_block, exec_output) = \
528 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
529 exec_template_base = 'Store')

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537 decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
538 decl_code += '\tbyte_offset ^= 3;\n'
539 decl_code += '#endif\n'
540
541 memacc_code = decl_code + memacc_code
542
543 (header_output, decoder_output, decode_block, exec_output) = \
544 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
545 decode_template = ImmNopCheckDecode,
546 exec_template_base = 'Load')
547}};
548
549def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
550 mem_flags = [], inst_flags = []) {{
551 decl_code = 'uint32_t mem_word = 0;\n'
552 decl_code += 'uint32_t unaligned_addr = Rs + disp;\n'
553 decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n'
554 decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
555 decl_code += '\tbyte_offset ^= 3;\n'
556 decl_code += '#endif\n'
557 decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n'
558 memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
559
560 (header_output, decoder_output, decode_block, exec_output) = \
561 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
562 exec_template_base = 'Store')
563}};
564
565def format Prefetch(ea_code = {{ EA = Rs + disp; }},
566 mem_flags = [], pf_flags = [], inst_flags = []) {{
567 pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
568 pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
569 'IsDataPrefetch', 'MemReadOp']

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