int.isa (3954:d689b611d9dc) int.isa (4661:44458219add1)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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29// Authors: Korey Sewell
30
31////////////////////////////////////////////////////////////////////
32//
33// Integer operate instructions
34//
35output header {{
36#include <iostream>
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 20 unchanged lines hidden (view full) ---

29// Authors: Korey Sewell
30
31////////////////////////////////////////////////////////////////////
32//
33// Integer operate instructions
34//
35output header {{
36#include <iostream>
37 using namespace std;
37 /**
38 * Base class for integer operations.
39 */
40 class IntOp : public MipsStaticInst
41 {
42 protected:
43
44 /// Constructor

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59 HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
60 IntOp(mnem, _machInst, __opClass)
61 {
62 }
63
64 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
65 };
66
38 /**
39 * Base class for integer operations.
40 */
41 class IntOp : public MipsStaticInst
42 {
43 protected:
44
45 /// Constructor

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60 HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
61 IntOp(mnem, _machInst, __opClass)
62 {
63 }
64
65 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
66 };
67
67 class HiLoMiscOp: public HiLoOp
68 class HiLoRsSelOp: public HiLoOp
68 {
69 protected:
70
71 /// Constructor
69 {
70 protected:
71
72 /// Constructor
72 HiLoMiscOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
73 HiLoRsSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
73 HiLoOp(mnem, _machInst, __opClass)
74 {
75 }
76
77 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
78 };
79
74 HiLoOp(mnem, _machInst, __opClass)
75 {
76 }
77
78 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
79 };
80
81 class HiLoRdSelOp: public HiLoOp
82 {
83 protected:
80
84
85 /// Constructor
86 HiLoRdSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
87 HiLoOp(mnem, _machInst, __opClass)
88 {
89 }
90
91 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
92 };
93
94 class HiLoRdSelValOp: public HiLoOp
95 {
96 protected:
97
98 /// Constructor
99 HiLoRdSelValOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
100 HiLoOp(mnem, _machInst, __opClass)
101 {
102 }
103
104 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
105 };
106
81 class IntImmOp : public MipsStaticInst
82 {
83 protected:
84
85 int16_t imm;
86 int32_t sextImm;
87 uint32_t zextImm;
88

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100
101 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
102
103
104 };
105
106}};
107
107 class IntImmOp : public MipsStaticInst
108 {
109 protected:
110
111 int16_t imm;
112 int32_t sextImm;
113 uint32_t zextImm;
114

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126
127 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
128
129
130 };
131
132}};
133
108// HiLo<Misc> instruction class execute method template.
109// Mainly to get instruction trace data to print out
110// correctly
134// HiLo instruction class execute method template.
111def template HiLoExecute {{
112 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
113 {
114 Fault fault = NoFault;
115
116 %(fp_enable_check)s;
117 %(op_decl)s;
118 %(op_rd)s;
119 %(code)s;
120
121 if(fault == NoFault)
122 {
123 %(op_wb)s;
135def template HiLoExecute {{
136 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
137 {
138 Fault fault = NoFault;
139
140 %(fp_enable_check)s;
141 %(op_decl)s;
142 %(op_rd)s;
143 %(code)s;
144
145 if(fault == NoFault)
146 {
147 %(op_wb)s;
124 //If there are 2 Destination Registers then
125 //concatenate the values for the traceData
126 if(traceData && _numDestRegs == 2) {
127 uint64_t hilo_final_val = (uint64_t)HI << 32 | LO;
128 traceData->setData(hilo_final_val);
129 }
130 }
131 return fault;
132 }
133}};
134
148 }
149 return fault;
150 }
151}};
152
153// HiLoRsSel instruction class execute method template.
154def template HiLoRsSelExecute {{
155 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
156 {
157 Fault fault = NoFault;
158
159 %(op_decl)s;
160
161 if( ACSRC > 0 && !isDspEnabled(xc) )
162 {
163 fault = new DspStateDisabledFault();
164 }
165 else
166 {
167 %(op_rd)s;
168 %(code)s;
169 }
170
171 if(fault == NoFault)
172 {
173 %(op_wb)s;
174 }
175 return fault;
176 }
177}};
178
179// HiLoRdSel instruction class execute method template.
180def template HiLoRdSelExecute {{
181 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
182 {
183 Fault fault = NoFault;
184
185 %(op_decl)s;
186
187 if( ACDST > 0 && !isDspEnabled(xc) )
188 {
189 fault = new DspStateDisabledFault();
190 }
191 else
192 {
193 %(op_rd)s;
194 %(code)s;
195 }
196
197 if(fault == NoFault)
198 {
199 %(op_wb)s;
200 }
201 return fault;
202 }
203}};
204
135//Outputs to decoder.cc
136output decoder {{
137 std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
138 {
139 std::stringstream ss;
140
141 ccprintf(ss, "%-10s ", mnemonic);
142

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176 if (_numSrcRegs > 1) {
177 ss << ", ";
178 printReg(ss, _srcRegIdx[1]);
179 }
180
181 return ss.str();
182 }
183
205//Outputs to decoder.cc
206output decoder {{
207 std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
208 {
209 std::stringstream ss;
210
211 ccprintf(ss, "%-10s ", mnemonic);
212

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246 if (_numSrcRegs > 1) {
247 ss << ", ";
248 printReg(ss, _srcRegIdx[1]);
249 }
250
251 return ss.str();
252 }
253
184 std::string HiLoMiscOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
254 std::string HiLoRsSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
185 {
186 std::stringstream ss;
187
188 ccprintf(ss, "%-10s ", mnemonic);
189
190 if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
191 printReg(ss, _destRegIdx[0]);
192 } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
193 printReg(ss, _srcRegIdx[0]);
194 }
195
196 return ss.str();
197 }
198
255 {
256 std::stringstream ss;
257
258 ccprintf(ss, "%-10s ", mnemonic);
259
260 if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
261 printReg(ss, _destRegIdx[0]);
262 } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
263 printReg(ss, _srcRegIdx[0]);
264 }
265
266 return ss.str();
267 }
268
269 std::string HiLoRdSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
270 {
271 std::stringstream ss;
272
273 ccprintf(ss, "%-10s ", mnemonic);
274
275 if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
276 printReg(ss, _destRegIdx[0]);
277 } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
278 printReg(ss, _srcRegIdx[0]);
279 }
280
281 return ss.str();
282 }
283
284 std::string HiLoRdSelValOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
285 {
286 std::stringstream ss;
287
288 ccprintf(ss, "%-10s ", mnemonic);
289
290 if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
291 printReg(ss, _destRegIdx[0]);
292 } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
293 printReg(ss, _srcRegIdx[0]);
294 }
295
296 return ss.str();
297 }
298
199 std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
200 {
201 std::stringstream ss;
202
203 ccprintf(ss, "%-10s ", mnemonic);
204
205 if (_numDestRegs > 0) {
206 printReg(ss, _destRegIdx[0]);

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234def format IntImmOp(code, *opt_flags) {{
235 iop = InstObjParams(name, Name, 'IntImmOp', code, opt_flags)
236 header_output = BasicDeclare.subst(iop)
237 decoder_output = BasicConstructor.subst(iop)
238 decode_block = ImmNopCheckDecode.subst(iop)
239 exec_output = BasicExecute.subst(iop)
240}};
241
299 std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
300 {
301 std::stringstream ss;
302
303 ccprintf(ss, "%-10s ", mnemonic);
304
305 if (_numDestRegs > 0) {
306 printReg(ss, _destRegIdx[0]);

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334def format IntImmOp(code, *opt_flags) {{
335 iop = InstObjParams(name, Name, 'IntImmOp', code, opt_flags)
336 header_output = BasicDeclare.subst(iop)
337 decoder_output = BasicConstructor.subst(iop)
338 decode_block = ImmNopCheckDecode.subst(iop)
339 exec_output = BasicExecute.subst(iop)
340}};
341
242def format HiLoOp(code, *opt_flags) {{
243 code += 'HI = val<63:32>;\n'
244 code += 'LO = val<31:0>;\n'
245
246 iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags)
342def format HiLoRsSelOp(code, *opt_flags) {{
343 iop = InstObjParams(name, Name, 'HiLoRsSelOp', code, opt_flags)
247 header_output = BasicDeclare.subst(iop)
248 decoder_output = BasicConstructor.subst(iop)
249 decode_block = BasicDecode.subst(iop)
344 header_output = BasicDeclare.subst(iop)
345 decoder_output = BasicConstructor.subst(iop)
346 decode_block = BasicDecode.subst(iop)
250 exec_output = HiLoExecute.subst(iop)
347 exec_output = HiLoRsSelExecute.subst(iop)
251}};
252
348}};
349
253def format HiLoMiscOp(code, *opt_flags) {{
254 iop = InstObjParams(name, Name, 'HiLoMiscOp', code, opt_flags)
350def format HiLoRdSelOp(code, *opt_flags) {{
351 iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
255 header_output = BasicDeclare.subst(iop)
256 decoder_output = BasicConstructor.subst(iop)
257 decode_block = BasicDecode.subst(iop)
352 header_output = BasicDeclare.subst(iop)
353 decoder_output = BasicConstructor.subst(iop)
354 decode_block = BasicDecode.subst(iop)
258 exec_output = BasicExecute.subst(iop)
355 exec_output = HiLoRdSelExecute.subst(iop)
259}};
260
356}};
357
358def format HiLoRdSelValOp(code, *opt_flags) {{
261
359
360 if '.sd' in code:
361 code = 'int64_t ' + code
362 elif '.ud' in code:
363 code = 'uint64_t ' + code
262
364
365 code += 'HI_RD_SEL = val<63:32>;\n'
366 code += 'LO_RD_SEL = val<31:0>;\n'
263
367
368 iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
369 header_output = BasicDeclare.subst(iop)
370 decoder_output = BasicConstructor.subst(iop)
371 decode_block = BasicDecode.subst(iop)
372 exec_output = HiLoRdSelExecute.subst(iop)
373}};
264
374
375def format HiLoOp(code, *opt_flags) {{
376 iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags)
377 header_output = BasicDeclare.subst(iop)
378 decoder_output = BasicConstructor.subst(iop)
379 decode_block = BasicDecode.subst(iop)
380 exec_output = HiLoExecute.subst(iop)
381}};