int.isa (2632:1bb2f91485ea) int.isa (2686:f0d591379ac3)
1// -*- mode:c++ -*-
2
3////////////////////////////////////////////////////////////////////
4//
5// Integer operate instructions
6//
1// -*- mode:c++ -*-
2
3////////////////////////////////////////////////////////////////////
4//
5// Integer operate instructions
6//
7
8//Outputs to decoder.hh
9output header {{
10#include <iostream>
11 using namespace std;
12 /**
13 * Base class for integer operations.
14 */
15 class IntOp : public MipsStaticInst
16 {
17 protected:
18
19 /// Constructor
20 IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
21 MipsStaticInst(mnem, _machInst, __opClass)
22 {
23 }
24
25 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
26 };
27
7output header {{
8#include <iostream>
9 using namespace std;
10 /**
11 * Base class for integer operations.
12 */
13 class IntOp : public MipsStaticInst
14 {
15 protected:
16
17 /// Constructor
18 IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
19 MipsStaticInst(mnem, _machInst, __opClass)
20 {
21 }
22
23 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
24 };
25
26
27 class HiLoOp: public IntOp
28 {
29 protected:
30
31 /// Constructor
32 HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
33 IntOp(mnem, _machInst, __opClass)
34 {
35 }
36
37 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
38 };
39
40 class HiLoMiscOp: public HiLoOp
41 {
42 protected:
43
44 /// Constructor
45 HiLoMiscOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
46 HiLoOp(mnem, _machInst, __opClass)
47 {
48 }
49
50 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
51 };
52
53
28 class IntImmOp : public MipsStaticInst
29 {
30 protected:
31
32 int16_t imm;
33 int32_t sextImm;
34 uint32_t zextImm;
35

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47
48 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
49
50
51 };
52
53}};
54
54 class IntImmOp : public MipsStaticInst
55 {
56 protected:
57
58 int16_t imm;
59 int32_t sextImm;
60 uint32_t zextImm;
61

--- 11 unchanged lines hidden (view full) ---

73
74 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
75
76
77 };
78
79}};
80
81// HiLo<Misc> instruction class execute method template.
82// Mainly to get instruction trace data to print out
83// correctly
84def template HiLoExecute {{
85 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
86 {
87 Fault fault = NoFault;
88
89 %(fp_enable_check)s;
90 %(op_decl)s;
91 %(op_rd)s;
92 %(code)s;
93
94 if(fault == NoFault)
95 {
96 %(op_wb)s;
97 //If there are 2 Destination Registers then
98 //concatenate the values for the traceData
99 if(traceData && _numDestRegs == 2) {
100 uint64_t hilo_final_val = (uint64_t)HI << 32 | LO;
101 traceData->setData(hilo_final_val);
102 }
103 }
104 return fault;
105 }
106}};
107
55//Outputs to decoder.cc
56output decoder {{
57 std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
58 {
59 std::stringstream ss;
60
61 ccprintf(ss, "%-10s ", mnemonic);
62
63 // just print the first dest... if there's a second one,
64 // it's generally implicit
65 if (_numDestRegs > 0) {
66 printReg(ss, _destRegIdx[0]);
108//Outputs to decoder.cc
109output decoder {{
110 std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
111 {
112 std::stringstream ss;
113
114 ccprintf(ss, "%-10s ", mnemonic);
115
116 // just print the first dest... if there's a second one,
117 // it's generally implicit
118 if (_numDestRegs > 0) {
119 printReg(ss, _destRegIdx[0]);
67 ss << ",";
120 ss << ", ";
68 }
69
70 // just print the first two source regs... if there's
71 // a third one, it's a read-modify-write dest (Rc),
72 // e.g. for CMOVxx
73 if (_numSrcRegs > 0) {
74 printReg(ss, _srcRegIdx[0]);
75 }
76
77 if (_numSrcRegs > 1) {
121 }
122
123 // just print the first two source regs... if there's
124 // a third one, it's a read-modify-write dest (Rc),
125 // e.g. for CMOVxx
126 if (_numSrcRegs > 0) {
127 printReg(ss, _srcRegIdx[0]);
128 }
129
130 if (_numSrcRegs > 1) {
78 ss << ",";
131 ss << ", ";
79 printReg(ss, _srcRegIdx[1]);
80 }
81
82 return ss.str();
83 }
84
132 printReg(ss, _srcRegIdx[1]);
133 }
134
135 return ss.str();
136 }
137
138 std::string HiLoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
139 {
140 std::stringstream ss;
141
142 ccprintf(ss, "%-10s ", mnemonic);
143
144 //Destination Registers are implicit for HI/LO ops
145 if (_numSrcRegs > 0) {
146 printReg(ss, _srcRegIdx[0]);
147 }
148
149 if (_numSrcRegs > 1) {
150 ss << ", ";
151 printReg(ss, _srcRegIdx[1]);
152 }
153
154 return ss.str();
155 }
156
157 std::string HiLoMiscOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
158 {
159 std::stringstream ss;
160
161 ccprintf(ss, "%-10s ", mnemonic);
162
163 if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
164 printReg(ss, _destRegIdx[0]);
165 } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
166 printReg(ss, _srcRegIdx[0]);
167 }
168
169 return ss.str();
170 }
171
85 std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
86 {
87 std::stringstream ss;
88
89 ccprintf(ss, "%-10s ", mnemonic);
90
91 if (_numDestRegs > 0) {
92 printReg(ss, _destRegIdx[0]);
93 }
94
172 std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
173 {
174 std::stringstream ss;
175
176 ccprintf(ss, "%-10s ", mnemonic);
177
178 if (_numDestRegs > 0) {
179 printReg(ss, _destRegIdx[0]);
180 }
181
95 ss << ",";
182 ss << ", ";
96
97 if (_numSrcRegs > 0) {
98 printReg(ss, _srcRegIdx[0]);
183
184 if (_numSrcRegs > 0) {
185 printReg(ss, _srcRegIdx[0]);
99 ss << ",";
186 ss << ", ";
100 }
101
102 if( mnemonic == "lui")
187 }
188
189 if( mnemonic == "lui")
103 ccprintf(ss, "%08p ", sextImm);
190 ccprintf(ss, "0x%x ", sextImm);
104 else
105 ss << (int) sextImm;
106
107 return ss.str();
108 }
109
110}};
111
191 else
192 ss << (int) sextImm;
193
194 return ss.str();
195 }
196
197}};
198
112//Used by decoder.isa
113def format IntOp(code, *opt_flags) {{
199def format IntOp(code, *opt_flags) {{
114 orig_code = code
115 cblk = CodeBlock(code)
200 iop = InstObjParams(name, Name, 'IntOp', CodeBlock(code), opt_flags)
201 header_output = BasicDeclare.subst(iop)
202 decoder_output = BasicConstructor.subst(iop)
203 decode_block = OperateNopCheckDecode.subst(iop)
204 exec_output = BasicExecute.subst(iop)
205}};
116
206
117 # Figure out if we are creating a IntImmOp or a IntOp
118 # by looking at the instruction name
119 iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
120 strlen = len(name)
121 if name[strlen-1] == 'i' or name[strlen-2:] == 'iu':
122 iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
207def format IntImmOp(code, *opt_flags) {{
208 iop = InstObjParams(name, Name, 'IntImmOp', CodeBlock(code), opt_flags)
209 header_output = BasicDeclare.subst(iop)
210 decoder_output = BasicConstructor.subst(iop)
211 decode_block = OperateNopCheckDecode.subst(iop)
212 exec_output = BasicExecute.subst(iop)
213}};
123
214
124 header_output = BasicDeclare.subst(iop)
125 decoder_output = BasicConstructor.subst(iop)
126 decode_block = OperateNopCheckDecode.subst(iop)
127 exec_output = BasicExecute.subst(iop)
215def format HiLoOp(code, *opt_flags) {{
216 if '.sd' in code:
217 code = 'int64_t ' + code
218 elif '.ud' in code:
219 code = 'uint64_t ' + code
220
221 code += 'HI = val<63:32>;\n'
222 code += 'LO = val<31:0>;\n'
223
224 iop = InstObjParams(name, Name, 'HiLoOp', CodeBlock(code), opt_flags)
225 header_output = BasicDeclare.subst(iop)
226 decoder_output = BasicConstructor.subst(iop)
227 decode_block = OperateNopCheckDecode.subst(iop)
228 exec_output = HiLoExecute.subst(iop)
128}};
129
229}};
230
231def format HiLoMiscOp(code, *opt_flags) {{
232 iop = InstObjParams(name, Name, 'HiLoMiscOp', CodeBlock(code), opt_flags)
233 header_output = BasicDeclare.subst(iop)
234 decoder_output = BasicConstructor.subst(iop)
235 decode_block = OperateNopCheckDecode.subst(iop)
236 exec_output = HiLoExecute.subst(iop)
237}};
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