| int.isa (12104:edd63f9c6184) | int.isa (12106:7784fac1b159) |
|---|---|
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 243 unchanged lines hidden (view full) --- 252 } 253 254 std::string HiLoRsSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 255 { 256 std::stringstream ss; 257 258 ccprintf(ss, "%-10s ", mnemonic); 259 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 243 unchanged lines hidden (view full) --- 252 } 253 254 std::string HiLoRsSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 255 { 256 std::stringstream ss; 257 258 ccprintf(ss, "%-10s ", mnemonic); 259 |
| 260 if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) { | 260 if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) { |
| 261 printReg(ss, _destRegIdx[0]); | 261 printReg(ss, _destRegIdx[0]); |
| 262 } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) { | 262 } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) { |
| 263 printReg(ss, _srcRegIdx[0]); 264 } 265 266 return ss.str(); 267 } 268 269 std::string HiLoRdSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 270 { 271 std::stringstream ss; 272 273 ccprintf(ss, "%-10s ", mnemonic); 274 | 263 printReg(ss, _srcRegIdx[0]); 264 } 265 266 return ss.str(); 267 } 268 269 std::string HiLoRdSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 270 { 271 std::stringstream ss; 272 273 ccprintf(ss, "%-10s ", mnemonic); 274 |
| 275 if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) { | 275 if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) { |
| 276 printReg(ss, _destRegIdx[0]); | 276 printReg(ss, _destRegIdx[0]); |
| 277 } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) { | 277 } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) { |
| 278 printReg(ss, _srcRegIdx[0]); 279 } 280 281 return ss.str(); 282 } 283 284 std::string HiLoRdSelValOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 285 { 286 std::stringstream ss; 287 288 ccprintf(ss, "%-10s ", mnemonic); 289 | 278 printReg(ss, _srcRegIdx[0]); 279 } 280 281 return ss.str(); 282 } 283 284 std::string HiLoRdSelValOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 285 { 286 std::stringstream ss; 287 288 ccprintf(ss, "%-10s ", mnemonic); 289 |
| 290 if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) { | 290 if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) { |
| 291 printReg(ss, _destRegIdx[0]); | 291 printReg(ss, _destRegIdx[0]); |
| 292 } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) { | 292 } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) { |
| 293 printReg(ss, _srcRegIdx[0]); 294 } 295 296 return ss.str(); 297 } 298 299 std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 300 { --- 81 unchanged lines hidden --- | 293 printReg(ss, _srcRegIdx[0]); 294 } 295 296 return ss.str(); 297 } 298 299 std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 300 { --- 81 unchanged lines hidden --- |