3////////////////////////////////////////////////////////////////////
4//
5// Integer operate instructions
6//
7output header {{
8#include <iostream>
9 using namespace std;
10 /**
11 * Base class for integer operations.
12 */
13 class IntOp : public MipsStaticInst
14 {
15 protected:
16
17 /// Constructor
18 IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
19 MipsStaticInst(mnem, _machInst, __opClass)
20 {
21 }
22
23 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
24 };
25
26
27 class HiLoOp: public IntOp
28 {
29 protected:
30
31 /// Constructor
32 HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
33 IntOp(mnem, _machInst, __opClass)
34 {
35 }
36
37 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
38 };
39
40 class HiLoMiscOp: public HiLoOp
41 {
42 protected:
43
44 /// Constructor
45 HiLoMiscOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
46 HiLoOp(mnem, _machInst, __opClass)
47 {
48 }
49
50 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
51 };
52
53
54 class IntImmOp : public MipsStaticInst
55 {
56 protected:
57
58 int16_t imm;
59 int32_t sextImm;
60 uint32_t zextImm;
61
62 /// Constructor
63 IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
64 MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM),
65 sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM)
66 {
67 //If Bit 15 is 1 then Sign Extend
68 int32_t temp = sextImm & 0x00008000;
69 if (temp > 0 && mnemonic != "lui") {
70 sextImm |= 0xFFFF0000;
71 }
72 }
73
74 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
75
76
77 };
78
79}};
80
81// HiLo<Misc> instruction class execute method template.
82// Mainly to get instruction trace data to print out
83// correctly
84def template HiLoExecute {{
85 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
86 {
87 Fault fault = NoFault;
88
89 %(fp_enable_check)s;
90 %(op_decl)s;
91 %(op_rd)s;
92 %(code)s;
93
94 if(fault == NoFault)
95 {
96 %(op_wb)s;
97 //If there are 2 Destination Registers then
98 //concatenate the values for the traceData
99 if(traceData && _numDestRegs == 2) {
100 uint64_t hilo_final_val = (uint64_t)HI << 32 | LO;
101 traceData->setData(hilo_final_val);
102 }
103 }
104 return fault;
105 }
106}};
107
108//Outputs to decoder.cc
109output decoder {{
110 std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
111 {
112 std::stringstream ss;
113
114 ccprintf(ss, "%-10s ", mnemonic);
115
116 // just print the first dest... if there's a second one,
117 // it's generally implicit
118 if (_numDestRegs > 0) {
119 printReg(ss, _destRegIdx[0]);
120 ss << ", ";
121 }
122
123 // just print the first two source regs... if there's
124 // a third one, it's a read-modify-write dest (Rc),
125 // e.g. for CMOVxx
126 if (_numSrcRegs > 0) {
127 printReg(ss, _srcRegIdx[0]);
128 }
129
130 if (_numSrcRegs > 1) {
131 ss << ", ";
132 printReg(ss, _srcRegIdx[1]);
133 }
134
135 return ss.str();
136 }
137
138 std::string HiLoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
139 {
140 std::stringstream ss;
141
142 ccprintf(ss, "%-10s ", mnemonic);
143
144 //Destination Registers are implicit for HI/LO ops
145 if (_numSrcRegs > 0) {
146 printReg(ss, _srcRegIdx[0]);
147 }
148
149 if (_numSrcRegs > 1) {
150 ss << ", ";
151 printReg(ss, _srcRegIdx[1]);
152 }
153
154 return ss.str();
155 }
156
157 std::string HiLoMiscOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
158 {
159 std::stringstream ss;
160
161 ccprintf(ss, "%-10s ", mnemonic);
162
163 if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
164 printReg(ss, _destRegIdx[0]);
165 } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
166 printReg(ss, _srcRegIdx[0]);
167 }
168
169 return ss.str();
170 }
171
172 std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
173 {
174 std::stringstream ss;
175
176 ccprintf(ss, "%-10s ", mnemonic);
177
178 if (_numDestRegs > 0) {
179 printReg(ss, _destRegIdx[0]);
180 }
181
182 ss << ", ";
183
184 if (_numSrcRegs > 0) {
185 printReg(ss, _srcRegIdx[0]);
186 ss << ", ";
187 }
188
189 if( mnemonic == "lui")
190 ccprintf(ss, "0x%x ", sextImm);
191 else
192 ss << (int) sextImm;
193
194 return ss.str();
195 }
196
197}};
198
199def format IntOp(code, *opt_flags) {{
200 iop = InstObjParams(name, Name, 'IntOp', CodeBlock(code), opt_flags)
201 header_output = BasicDeclare.subst(iop)
202 decoder_output = BasicConstructor.subst(iop)
203 decode_block = OperateNopCheckDecode.subst(iop)
204 exec_output = BasicExecute.subst(iop)
205}};
206
207def format IntImmOp(code, *opt_flags) {{
208 iop = InstObjParams(name, Name, 'IntImmOp', CodeBlock(code), opt_flags)
209 header_output = BasicDeclare.subst(iop)
210 decoder_output = BasicConstructor.subst(iop)
211 decode_block = OperateNopCheckDecode.subst(iop)
212 exec_output = BasicExecute.subst(iop)
213}};
214
215def format HiLoOp(code, *opt_flags) {{
216 if '.sd' in code:
217 code = 'int64_t ' + code
218 elif '.ud' in code:
219 code = 'uint64_t ' + code
220
221 code += 'HI = val<63:32>;\n'
222 code += 'LO = val<31:0>;\n'
223
224 iop = InstObjParams(name, Name, 'HiLoOp', CodeBlock(code), opt_flags)
225 header_output = BasicDeclare.subst(iop)
226 decoder_output = BasicConstructor.subst(iop)
227 decode_block = OperateNopCheckDecode.subst(iop)
228 exec_output = HiLoExecute.subst(iop)
229}};
230
231def format HiLoMiscOp(code, *opt_flags) {{
232 iop = InstObjParams(name, Name, 'HiLoMiscOp', CodeBlock(code), opt_flags)
233 header_output = BasicDeclare.subst(iop)
234 decoder_output = BasicConstructor.subst(iop)
235 decode_block = OperateNopCheckDecode.subst(iop)
236 exec_output = HiLoExecute.subst(iop)
237}};
238
239
240
241
242
| 31////////////////////////////////////////////////////////////////////
32//
33// Integer operate instructions
34//
35output header {{
36#include <iostream>
37 using namespace std;
38 /**
39 * Base class for integer operations.
40 */
41 class IntOp : public MipsStaticInst
42 {
43 protected:
44
45 /// Constructor
46 IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
47 MipsStaticInst(mnem, _machInst, __opClass)
48 {
49 }
50
51 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
52 };
53
54
55 class HiLoOp: public IntOp
56 {
57 protected:
58
59 /// Constructor
60 HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
61 IntOp(mnem, _machInst, __opClass)
62 {
63 }
64
65 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
66 };
67
68 class HiLoMiscOp: public HiLoOp
69 {
70 protected:
71
72 /// Constructor
73 HiLoMiscOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
74 HiLoOp(mnem, _machInst, __opClass)
75 {
76 }
77
78 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
79 };
80
81
82 class IntImmOp : public MipsStaticInst
83 {
84 protected:
85
86 int16_t imm;
87 int32_t sextImm;
88 uint32_t zextImm;
89
90 /// Constructor
91 IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
92 MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM),
93 sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM)
94 {
95 //If Bit 15 is 1 then Sign Extend
96 int32_t temp = sextImm & 0x00008000;
97 if (temp > 0 && mnemonic != "lui") {
98 sextImm |= 0xFFFF0000;
99 }
100 }
101
102 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
103
104
105 };
106
107}};
108
109// HiLo<Misc> instruction class execute method template.
110// Mainly to get instruction trace data to print out
111// correctly
112def template HiLoExecute {{
113 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
114 {
115 Fault fault = NoFault;
116
117 %(fp_enable_check)s;
118 %(op_decl)s;
119 %(op_rd)s;
120 %(code)s;
121
122 if(fault == NoFault)
123 {
124 %(op_wb)s;
125 //If there are 2 Destination Registers then
126 //concatenate the values for the traceData
127 if(traceData && _numDestRegs == 2) {
128 uint64_t hilo_final_val = (uint64_t)HI << 32 | LO;
129 traceData->setData(hilo_final_val);
130 }
131 }
132 return fault;
133 }
134}};
135
136//Outputs to decoder.cc
137output decoder {{
138 std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
139 {
140 std::stringstream ss;
141
142 ccprintf(ss, "%-10s ", mnemonic);
143
144 // just print the first dest... if there's a second one,
145 // it's generally implicit
146 if (_numDestRegs > 0) {
147 printReg(ss, _destRegIdx[0]);
148 ss << ", ";
149 }
150
151 // just print the first two source regs... if there's
152 // a third one, it's a read-modify-write dest (Rc),
153 // e.g. for CMOVxx
154 if (_numSrcRegs > 0) {
155 printReg(ss, _srcRegIdx[0]);
156 }
157
158 if (_numSrcRegs > 1) {
159 ss << ", ";
160 printReg(ss, _srcRegIdx[1]);
161 }
162
163 return ss.str();
164 }
165
166 std::string HiLoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
167 {
168 std::stringstream ss;
169
170 ccprintf(ss, "%-10s ", mnemonic);
171
172 //Destination Registers are implicit for HI/LO ops
173 if (_numSrcRegs > 0) {
174 printReg(ss, _srcRegIdx[0]);
175 }
176
177 if (_numSrcRegs > 1) {
178 ss << ", ";
179 printReg(ss, _srcRegIdx[1]);
180 }
181
182 return ss.str();
183 }
184
185 std::string HiLoMiscOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
186 {
187 std::stringstream ss;
188
189 ccprintf(ss, "%-10s ", mnemonic);
190
191 if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
192 printReg(ss, _destRegIdx[0]);
193 } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
194 printReg(ss, _srcRegIdx[0]);
195 }
196
197 return ss.str();
198 }
199
200 std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
201 {
202 std::stringstream ss;
203
204 ccprintf(ss, "%-10s ", mnemonic);
205
206 if (_numDestRegs > 0) {
207 printReg(ss, _destRegIdx[0]);
208 }
209
210 ss << ", ";
211
212 if (_numSrcRegs > 0) {
213 printReg(ss, _srcRegIdx[0]);
214 ss << ", ";
215 }
216
217 if( mnemonic == "lui")
218 ccprintf(ss, "0x%x ", sextImm);
219 else
220 ss << (int) sextImm;
221
222 return ss.str();
223 }
224
225}};
226
227def format IntOp(code, *opt_flags) {{
228 iop = InstObjParams(name, Name, 'IntOp', CodeBlock(code), opt_flags)
229 header_output = BasicDeclare.subst(iop)
230 decoder_output = BasicConstructor.subst(iop)
231 decode_block = OperateNopCheckDecode.subst(iop)
232 exec_output = BasicExecute.subst(iop)
233}};
234
235def format IntImmOp(code, *opt_flags) {{
236 iop = InstObjParams(name, Name, 'IntImmOp', CodeBlock(code), opt_flags)
237 header_output = BasicDeclare.subst(iop)
238 decoder_output = BasicConstructor.subst(iop)
239 decode_block = OperateNopCheckDecode.subst(iop)
240 exec_output = BasicExecute.subst(iop)
241}};
242
243def format HiLoOp(code, *opt_flags) {{
244 if '.sd' in code:
245 code = 'int64_t ' + code
246 elif '.ud' in code:
247 code = 'uint64_t ' + code
248
249 code += 'HI = val<63:32>;\n'
250 code += 'LO = val<31:0>;\n'
251
252 iop = InstObjParams(name, Name, 'HiLoOp', CodeBlock(code), opt_flags)
253 header_output = BasicDeclare.subst(iop)
254 decoder_output = BasicConstructor.subst(iop)
255 decode_block = OperateNopCheckDecode.subst(iop)
256 exec_output = HiLoExecute.subst(iop)
257}};
258
259def format HiLoMiscOp(code, *opt_flags) {{
260 iop = InstObjParams(name, Name, 'HiLoMiscOp', CodeBlock(code), opt_flags)
261 header_output = BasicDeclare.subst(iop)
262 decoder_output = BasicConstructor.subst(iop)
263 decode_block = OperateNopCheckDecode.subst(iop)
264 exec_output = HiLoExecute.subst(iop)
265}};
266
267
268
269
270
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