1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30
31////////////////////////////////////////////////////////////////////
32//
33// Integer operate instructions
34//
35output header {{
36#include <iostream>
37 using namespace std;
38 /**
39 * Base class for integer operations.
40 */
41 class IntOp : public MipsStaticInst
42 {
43 protected:
44
45 /// Constructor
46 IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
47 MipsStaticInst(mnem, _machInst, __opClass)
48 {
49 }
50
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30
31////////////////////////////////////////////////////////////////////
32//
33// Integer operate instructions
34//
35output header {{
36#include <iostream>
37 using namespace std;
38 /**
39 * Base class for integer operations.
40 */
41 class IntOp : public MipsStaticInst
42 {
43 protected:
44
45 /// Constructor
46 IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
47 MipsStaticInst(mnem, _machInst, __opClass)
48 {
49 }
50
|
51 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 51 std::string generateDisassembly(
52 Addr pc, const SymbolTable *symtab) const override;
|
52 };
53
54
55 class HiLoOp: public IntOp
56 {
57 protected:
58
59 /// Constructor
60 HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
61 IntOp(mnem, _machInst, __opClass)
62 {
63 }
64
| 53 };
54
55
56 class HiLoOp: public IntOp
57 {
58 protected:
59
60 /// Constructor
61 HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
62 IntOp(mnem, _machInst, __opClass)
63 {
64 }
65
|
65 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 66 std::string generateDisassembly(
67 Addr pc, const SymbolTable *symtab) const override;
|
66 };
67
68 class HiLoRsSelOp: public HiLoOp
69 {
70 protected:
71
72 /// Constructor
73 HiLoRsSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
74 HiLoOp(mnem, _machInst, __opClass)
75 {
76 }
77
| 68 };
69
70 class HiLoRsSelOp: public HiLoOp
71 {
72 protected:
73
74 /// Constructor
75 HiLoRsSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
76 HiLoOp(mnem, _machInst, __opClass)
77 {
78 }
79
|
78 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 80 std::string generateDisassembly(
81 Addr pc, const SymbolTable *symtab) const override;
|
79 };
80
81 class HiLoRdSelOp: public HiLoOp
82 {
83 protected:
84
85 /// Constructor
86 HiLoRdSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
87 HiLoOp(mnem, _machInst, __opClass)
88 {
89 }
90
| 82 };
83
84 class HiLoRdSelOp: public HiLoOp
85 {
86 protected:
87
88 /// Constructor
89 HiLoRdSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
90 HiLoOp(mnem, _machInst, __opClass)
91 {
92 }
93
|
91 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 94 std::string generateDisassembly(
95 Addr pc, const SymbolTable *symtab) const override;
|
92 };
93
94 class HiLoRdSelValOp: public HiLoOp
95 {
96 protected:
97
98 /// Constructor
99 HiLoRdSelValOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
100 HiLoOp(mnem, _machInst, __opClass)
101 {
102 }
103
| 96 };
97
98 class HiLoRdSelValOp: public HiLoOp
99 {
100 protected:
101
102 /// Constructor
103 HiLoRdSelValOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
104 HiLoOp(mnem, _machInst, __opClass)
105 {
106 }
107
|
104 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 108 std::string generateDisassembly(
109 Addr pc, const SymbolTable *symtab) const override;
|
105 };
106
107 class IntImmOp : public MipsStaticInst
108 {
109 protected:
110
111 int16_t imm;
112 int32_t sextImm;
113 uint32_t zextImm;
114
115 /// Constructor
116 IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
117 MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM),
118 sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM)
119 {
120 //If Bit 15 is 1 then Sign Extend
121 int32_t temp = sextImm & 0x00008000;
122 if (temp > 0 && strcmp(mnemonic,"lui") != 0) {
123 sextImm |= 0xFFFF0000;
124 }
125 }
126
| 110 };
111
112 class IntImmOp : public MipsStaticInst
113 {
114 protected:
115
116 int16_t imm;
117 int32_t sextImm;
118 uint32_t zextImm;
119
120 /// Constructor
121 IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
122 MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM),
123 sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM)
124 {
125 //If Bit 15 is 1 then Sign Extend
126 int32_t temp = sextImm & 0x00008000;
127 if (temp > 0 && strcmp(mnemonic,"lui") != 0) {
128 sextImm |= 0xFFFF0000;
129 }
130 }
131
|
127 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
128
129
| 132 std::string generateDisassembly(
133 Addr pc, const SymbolTable *symtab) const override;
|
130 };
131
132}};
133
134// HiLo instruction class execute method template.
135def template HiLoExecute {{
136 Fault %(class_name)s::execute(
137 ExecContext *xc, Trace::InstRecord *traceData) const
138 {
139 Fault fault = NoFault;
140
141 %(fp_enable_check)s;
142 %(op_decl)s;
143 %(op_rd)s;
144 %(code)s;
145
146 if(fault == NoFault)
147 {
148 %(op_wb)s;
149 }
150 return fault;
151 }
152}};
153
154// HiLoRsSel instruction class execute method template.
155def template HiLoRsSelExecute {{
156 Fault %(class_name)s::execute(
157 ExecContext *xc, Trace::InstRecord *traceData) const
158 {
159 Fault fault = NoFault;
160
161 %(op_decl)s;
162
163 if( ACSRC > 0 && !isDspEnabled(xc) )
164 {
165 fault = std::make_shared<DspStateDisabledFault>();
166 }
167 else
168 {
169 %(op_rd)s;
170 %(code)s;
171 }
172
173 if(fault == NoFault)
174 {
175 %(op_wb)s;
176 }
177 return fault;
178 }
179}};
180
181// HiLoRdSel instruction class execute method template.
182def template HiLoRdSelExecute {{
183 Fault %(class_name)s::execute(
184 ExecContext *xc, Trace::InstRecord *traceData) const
185 {
186 Fault fault = NoFault;
187
188 %(op_decl)s;
189
190 if( ACDST > 0 && !isDspEnabled(xc) )
191 {
192 fault = std::make_shared<DspStateDisabledFault>();
193 }
194 else
195 {
196 %(op_rd)s;
197 %(code)s;
198 }
199
200 if(fault == NoFault)
201 {
202 %(op_wb)s;
203 }
204 return fault;
205 }
206}};
207
208//Outputs to decoder.cc
209output decoder {{
210 std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
211 {
212 std::stringstream ss;
213
214 ccprintf(ss, "%-10s ", mnemonic);
215
216 // just print the first dest... if there's a second one,
217 // it's generally implicit
218 if (_numDestRegs > 0) {
219 printReg(ss, _destRegIdx[0]);
220 ss << ", ";
221 }
222
223 // just print the first two source regs... if there's
224 // a third one, it's a read-modify-write dest (Rc),
225 // e.g. for CMOVxx
226 if (_numSrcRegs > 0) {
227 printReg(ss, _srcRegIdx[0]);
228 }
229
230 if (_numSrcRegs > 1) {
231 ss << ", ";
232 printReg(ss, _srcRegIdx[1]);
233 }
234
235 return ss.str();
236 }
237
238 std::string HiLoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
239 {
240 std::stringstream ss;
241
242 ccprintf(ss, "%-10s ", mnemonic);
243
244 //Destination Registers are implicit for HI/LO ops
245 if (_numSrcRegs > 0) {
246 printReg(ss, _srcRegIdx[0]);
247 }
248
249 if (_numSrcRegs > 1) {
250 ss << ", ";
251 printReg(ss, _srcRegIdx[1]);
252 }
253
254 return ss.str();
255 }
256
257 std::string HiLoRsSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
258 {
259 std::stringstream ss;
260
261 ccprintf(ss, "%-10s ", mnemonic);
262
263 if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
264 printReg(ss, _destRegIdx[0]);
265 } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
266 printReg(ss, _srcRegIdx[0]);
267 }
268
269 return ss.str();
270 }
271
272 std::string HiLoRdSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
273 {
274 std::stringstream ss;
275
276 ccprintf(ss, "%-10s ", mnemonic);
277
278 if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
279 printReg(ss, _destRegIdx[0]);
280 } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
281 printReg(ss, _srcRegIdx[0]);
282 }
283
284 return ss.str();
285 }
286
287 std::string HiLoRdSelValOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
288 {
289 std::stringstream ss;
290
291 ccprintf(ss, "%-10s ", mnemonic);
292
293 if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
294 printReg(ss, _destRegIdx[0]);
295 } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
296 printReg(ss, _srcRegIdx[0]);
297 }
298
299 return ss.str();
300 }
301
302 std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
303 {
304 std::stringstream ss;
305
306 ccprintf(ss, "%-10s ", mnemonic);
307
308 if (_numDestRegs > 0) {
309 printReg(ss, _destRegIdx[0]);
310 }
311
312 ss << ", ";
313
314 if (_numSrcRegs > 0) {
315 printReg(ss, _srcRegIdx[0]);
316 ss << ", ";
317 }
318
319 if(strcmp(mnemonic,"lui") == 0)
320 ccprintf(ss, "0x%x ", sextImm);
321 else
322 ss << (int) sextImm;
323
324 return ss.str();
325 }
326
327}};
328
329def format IntOp(code, *opt_flags) {{
330 iop = InstObjParams(name, Name, 'IntOp', code, opt_flags)
331 header_output = BasicDeclare.subst(iop)
332 decoder_output = BasicConstructor.subst(iop)
333 decode_block = RegNopCheckDecode.subst(iop)
334 exec_output = BasicExecute.subst(iop)
335}};
336
337def format IntImmOp(code, *opt_flags) {{
338 iop = InstObjParams(name, Name, 'IntImmOp', code, opt_flags)
339 header_output = BasicDeclare.subst(iop)
340 decoder_output = BasicConstructor.subst(iop)
341 decode_block = ImmNopCheckDecode.subst(iop)
342 exec_output = BasicExecute.subst(iop)
343}};
344
345def format HiLoRsSelOp(code, *opt_flags) {{
346 iop = InstObjParams(name, Name, 'HiLoRsSelOp', code, opt_flags)
347 header_output = BasicDeclare.subst(iop)
348 decoder_output = BasicConstructor.subst(iop)
349 decode_block = BasicDecode.subst(iop)
350 exec_output = HiLoRsSelExecute.subst(iop)
351}};
352
353def format HiLoRdSelOp(code, *opt_flags) {{
354 iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
355 header_output = BasicDeclare.subst(iop)
356 decoder_output = BasicConstructor.subst(iop)
357 decode_block = BasicDecode.subst(iop)
358 exec_output = HiLoRdSelExecute.subst(iop)
359}};
360
361def format HiLoRdSelValOp(code, *opt_flags) {{
362
363 if '_sd' in code:
364 code = 'int64_t ' + code
365 elif '_ud' in code:
366 code = 'uint64_t ' + code
367
368 code += 'HI_RD_SEL = val<63:32>;\n'
369 code += 'LO_RD_SEL = val<31:0>;\n'
370
371 iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
372 header_output = BasicDeclare.subst(iop)
373 decoder_output = BasicConstructor.subst(iop)
374 decode_block = BasicDecode.subst(iop)
375 exec_output = HiLoRdSelExecute.subst(iop)
376}};
377
378def format HiLoOp(code, *opt_flags) {{
379 iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags)
380 header_output = BasicDeclare.subst(iop)
381 decoder_output = BasicConstructor.subst(iop)
382 decode_block = BasicDecode.subst(iop)
383 exec_output = HiLoExecute.subst(iop)
384}};
| 134 };
135
136}};
137
138// HiLo instruction class execute method template.
139def template HiLoExecute {{
140 Fault %(class_name)s::execute(
141 ExecContext *xc, Trace::InstRecord *traceData) const
142 {
143 Fault fault = NoFault;
144
145 %(fp_enable_check)s;
146 %(op_decl)s;
147 %(op_rd)s;
148 %(code)s;
149
150 if(fault == NoFault)
151 {
152 %(op_wb)s;
153 }
154 return fault;
155 }
156}};
157
158// HiLoRsSel instruction class execute method template.
159def template HiLoRsSelExecute {{
160 Fault %(class_name)s::execute(
161 ExecContext *xc, Trace::InstRecord *traceData) const
162 {
163 Fault fault = NoFault;
164
165 %(op_decl)s;
166
167 if( ACSRC > 0 && !isDspEnabled(xc) )
168 {
169 fault = std::make_shared<DspStateDisabledFault>();
170 }
171 else
172 {
173 %(op_rd)s;
174 %(code)s;
175 }
176
177 if(fault == NoFault)
178 {
179 %(op_wb)s;
180 }
181 return fault;
182 }
183}};
184
185// HiLoRdSel instruction class execute method template.
186def template HiLoRdSelExecute {{
187 Fault %(class_name)s::execute(
188 ExecContext *xc, Trace::InstRecord *traceData) const
189 {
190 Fault fault = NoFault;
191
192 %(op_decl)s;
193
194 if( ACDST > 0 && !isDspEnabled(xc) )
195 {
196 fault = std::make_shared<DspStateDisabledFault>();
197 }
198 else
199 {
200 %(op_rd)s;
201 %(code)s;
202 }
203
204 if(fault == NoFault)
205 {
206 %(op_wb)s;
207 }
208 return fault;
209 }
210}};
211
212//Outputs to decoder.cc
213output decoder {{
214 std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
215 {
216 std::stringstream ss;
217
218 ccprintf(ss, "%-10s ", mnemonic);
219
220 // just print the first dest... if there's a second one,
221 // it's generally implicit
222 if (_numDestRegs > 0) {
223 printReg(ss, _destRegIdx[0]);
224 ss << ", ";
225 }
226
227 // just print the first two source regs... if there's
228 // a third one, it's a read-modify-write dest (Rc),
229 // e.g. for CMOVxx
230 if (_numSrcRegs > 0) {
231 printReg(ss, _srcRegIdx[0]);
232 }
233
234 if (_numSrcRegs > 1) {
235 ss << ", ";
236 printReg(ss, _srcRegIdx[1]);
237 }
238
239 return ss.str();
240 }
241
242 std::string HiLoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
243 {
244 std::stringstream ss;
245
246 ccprintf(ss, "%-10s ", mnemonic);
247
248 //Destination Registers are implicit for HI/LO ops
249 if (_numSrcRegs > 0) {
250 printReg(ss, _srcRegIdx[0]);
251 }
252
253 if (_numSrcRegs > 1) {
254 ss << ", ";
255 printReg(ss, _srcRegIdx[1]);
256 }
257
258 return ss.str();
259 }
260
261 std::string HiLoRsSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
262 {
263 std::stringstream ss;
264
265 ccprintf(ss, "%-10s ", mnemonic);
266
267 if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
268 printReg(ss, _destRegIdx[0]);
269 } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
270 printReg(ss, _srcRegIdx[0]);
271 }
272
273 return ss.str();
274 }
275
276 std::string HiLoRdSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
277 {
278 std::stringstream ss;
279
280 ccprintf(ss, "%-10s ", mnemonic);
281
282 if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
283 printReg(ss, _destRegIdx[0]);
284 } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
285 printReg(ss, _srcRegIdx[0]);
286 }
287
288 return ss.str();
289 }
290
291 std::string HiLoRdSelValOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
292 {
293 std::stringstream ss;
294
295 ccprintf(ss, "%-10s ", mnemonic);
296
297 if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
298 printReg(ss, _destRegIdx[0]);
299 } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
300 printReg(ss, _srcRegIdx[0]);
301 }
302
303 return ss.str();
304 }
305
306 std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
307 {
308 std::stringstream ss;
309
310 ccprintf(ss, "%-10s ", mnemonic);
311
312 if (_numDestRegs > 0) {
313 printReg(ss, _destRegIdx[0]);
314 }
315
316 ss << ", ";
317
318 if (_numSrcRegs > 0) {
319 printReg(ss, _srcRegIdx[0]);
320 ss << ", ";
321 }
322
323 if(strcmp(mnemonic,"lui") == 0)
324 ccprintf(ss, "0x%x ", sextImm);
325 else
326 ss << (int) sextImm;
327
328 return ss.str();
329 }
330
331}};
332
333def format IntOp(code, *opt_flags) {{
334 iop = InstObjParams(name, Name, 'IntOp', code, opt_flags)
335 header_output = BasicDeclare.subst(iop)
336 decoder_output = BasicConstructor.subst(iop)
337 decode_block = RegNopCheckDecode.subst(iop)
338 exec_output = BasicExecute.subst(iop)
339}};
340
341def format IntImmOp(code, *opt_flags) {{
342 iop = InstObjParams(name, Name, 'IntImmOp', code, opt_flags)
343 header_output = BasicDeclare.subst(iop)
344 decoder_output = BasicConstructor.subst(iop)
345 decode_block = ImmNopCheckDecode.subst(iop)
346 exec_output = BasicExecute.subst(iop)
347}};
348
349def format HiLoRsSelOp(code, *opt_flags) {{
350 iop = InstObjParams(name, Name, 'HiLoRsSelOp', code, opt_flags)
351 header_output = BasicDeclare.subst(iop)
352 decoder_output = BasicConstructor.subst(iop)
353 decode_block = BasicDecode.subst(iop)
354 exec_output = HiLoRsSelExecute.subst(iop)
355}};
356
357def format HiLoRdSelOp(code, *opt_flags) {{
358 iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
359 header_output = BasicDeclare.subst(iop)
360 decoder_output = BasicConstructor.subst(iop)
361 decode_block = BasicDecode.subst(iop)
362 exec_output = HiLoRdSelExecute.subst(iop)
363}};
364
365def format HiLoRdSelValOp(code, *opt_flags) {{
366
367 if '_sd' in code:
368 code = 'int64_t ' + code
369 elif '_ud' in code:
370 code = 'uint64_t ' + code
371
372 code += 'HI_RD_SEL = val<63:32>;\n'
373 code += 'LO_RD_SEL = val<31:0>;\n'
374
375 iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
376 header_output = BasicDeclare.subst(iop)
377 decoder_output = BasicConstructor.subst(iop)
378 decode_block = BasicDecode.subst(iop)
379 exec_output = HiLoRdSelExecute.subst(iop)
380}};
381
382def format HiLoOp(code, *opt_flags) {{
383 iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags)
384 header_output = BasicDeclare.subst(iop)
385 decoder_output = BasicConstructor.subst(iop)
386 decode_block = BasicDecode.subst(iop)
387 exec_output = HiLoExecute.subst(iop)
388}};
|