fp.isa (9999:fdd2d34b0871) fp.isa (10196:be0e1724eb39)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 78 unchanged lines hidden (view full) ---

87}};
88
89output header {{
90 void fpResetCauseBits(%(CPU_exec_context)s *cpu);
91
92}};
93
94output exec {{
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 78 unchanged lines hidden (view full) ---

87}};
88
89output header {{
90 void fpResetCauseBits(%(CPU_exec_context)s *cpu);
91
92}};
93
94output exec {{
95 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
95 inline Fault checkFpEnableFault(CPU_EXEC_CONTEXT *xc)
96 {
97 //@TODO: Implement correct CP0 checks to see if the CP1
98 // unit is enable or not
99 if (!isCoprocessorEnabled(xc, 1))
100 return new CoprocessorUnusableFault(1);
101
102 return NoFault;
103 }
104
105 //If any operand is Nan return the appropriate QNaN
106 template <class T>
107 bool
96 {
97 //@TODO: Implement correct CP0 checks to see if the CP1
98 // unit is enable or not
99 if (!isCoprocessorEnabled(xc, 1))
100 return new CoprocessorUnusableFault(1);
101
102 return NoFault;
103 }
104
105 //If any operand is Nan return the appropriate QNaN
106 template <class T>
107 bool
108 fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type,
108 fpNanOperands(FPOp *inst, CPU_EXEC_CONTEXT *xc, const T &src_type,
109 Trace::InstRecord *traceData)
110 {
111 uint64_t mips_nan = 0;
112 assert(sizeof(T) == 4);
113
114 for (int i = 0; i < inst->numSrcRegs(); i++) {
115 uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0);
116

--- 4 unchanged lines hidden (view full) ---

121 return true;
122 }
123 }
124 return false;
125 }
126
127 template <class T>
128 bool
109 Trace::InstRecord *traceData)
110 {
111 uint64_t mips_nan = 0;
112 assert(sizeof(T) == 4);
113
114 for (int i = 0; i < inst->numSrcRegs(); i++) {
115 uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0);
116

--- 4 unchanged lines hidden (view full) ---

121 return true;
122 }
123 }
124 return false;
125 }
126
127 template <class T>
128 bool
129 fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
129 fpInvalidOp(FPOp *inst, CPU_EXEC_CONTEXT *cpu, const T dest_val,
130 Trace::InstRecord *traceData)
131 {
132 uint64_t mips_nan = 0;
133 T src_op = dest_val;
134 assert(sizeof(T) == 4);
135
136 if (isNan(&src_op, 32)) {
137 mips_nan = MIPS32_QNAN;

--- 13 unchanged lines hidden (view full) ---

151 if (traceData) { traceData->setData(mips_nan); }
152 return true;
153 }
154
155 return false;
156 }
157
158 void
130 Trace::InstRecord *traceData)
131 {
132 uint64_t mips_nan = 0;
133 T src_op = dest_val;
134 assert(sizeof(T) == 4);
135
136 if (isNan(&src_op, 32)) {
137 mips_nan = MIPS32_QNAN;

--- 13 unchanged lines hidden (view full) ---

151 if (traceData) { traceData->setData(mips_nan); }
152 return true;
153 }
154
155 return false;
156 }
157
158 void
159 fpResetCauseBits(%(CPU_exec_context)s *cpu)
159 fpResetCauseBits(CPU_EXEC_CONTEXT *cpu)
160 {
161 //Read FCSR from FloatRegFile
162 uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
163
164 // TODO: Use utility function here
165 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
166
167 //Write FCSR from FloatRegFile
168 cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr);
169 }
170}};
171
172def template FloatingPointExecute {{
160 {
161 //Read FCSR from FloatRegFile
162 uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
163
164 // TODO: Use utility function here
165 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
166
167 //Write FCSR from FloatRegFile
168 cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr);
169 }
170}};
171
172def template FloatingPointExecute {{
173 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
173 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
174 {
175 Fault fault = NoFault;
176
177 %(fp_enable_check)s;
178
179
180 //When is the right time to reset cause bits?
181 //start of every instruction or every cycle?

--- 194 unchanged lines hidden --- 		174 {
175 Fault fault = NoFault;
176
177 %(fp_enable_check)s;
178
179
180 //When is the right time to reset cause bits?
181 //start of every instruction or every cycle?

--- 194 unchanged lines hidden ---