fp.isa (6314:781969fbeca9) fp.isa (6383:31c067ae3331)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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130
131 if (isNan(&src_op, 32)) {
132 mips_nan = MIPS32_QNAN;
133
134 //Set value to QNAN
135 cpu->setFloatRegOperandBits(inst, 0, mips_nan);
136
137 //Read FCSR from FloatRegFile
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 121 unchanged lines hidden (view full) ---

130
131 if (isNan(&src_op, 32)) {
132 mips_nan = MIPS32_QNAN;
133
134 //Set value to QNAN
135 cpu->setFloatRegOperandBits(inst, 0, mips_nan);
136
137 //Read FCSR from FloatRegFile
138 uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
138 uint32_t fcsr_bits =
139 cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
139
140 uint32_t new_fcsr = genInvalidVector(fcsr_bits);
141
142 //Write FCSR from FloatRegFile
140
141 uint32_t new_fcsr = genInvalidVector(fcsr_bits);
142
143 //Write FCSR from FloatRegFile
143 cpu->tcBase()->setFloatRegBits(FCSR, new_fcsr);
144 cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, new_fcsr);
144
145 if (traceData) { traceData->setData(mips_nan); }
146 return true;
147 }
148
149 return false;
150 }
151
152 void
153 fpResetCauseBits(%(CPU_exec_context)s *cpu)
154 {
155 //Read FCSR from FloatRegFile
145
146 if (traceData) { traceData->setData(mips_nan); }
147 return true;
148 }
149
150 return false;
151 }
152
153 void
154 fpResetCauseBits(%(CPU_exec_context)s *cpu)
155 {
156 //Read FCSR from FloatRegFile
156 uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR);
157 uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
157
158 // TODO: Use utility function here
159 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
160
161 //Write FCSR from FloatRegFile
158
159 // TODO: Use utility function here
160 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
161
162 //Write FCSR from FloatRegFile
162 cpu->tcBase()->setFloatRegBits(FCSR, fcsr);
163 cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr);
163 }
164}};
165
166def template FloatingPointExecute {{
167 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
168 {
169 Fault fault = NoFault;
170

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165}};
166
167def template FloatingPointExecute {{
168 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
169 {
170 Fault fault = NoFault;
171

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