fp.isa (5268:5bfc53fe60e7) fp.isa (6314:781969fbeca9)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 90 unchanged lines hidden (view full) ---

99
100 //If any operand is Nan return the appropriate QNaN
101 template <class T>
102 bool
103 fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type,
104 Trace::InstRecord *traceData)
105 {
106 uint64_t mips_nan = 0;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 90 unchanged lines hidden (view full) ---

99
100 //If any operand is Nan return the appropriate QNaN
101 template <class T>
102 bool
103 fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type,
104 Trace::InstRecord *traceData)
105 {
106 uint64_t mips_nan = 0;
107 T src_op = 0;
108 int size = sizeof(src_op) * 8;
107 assert(sizeof(T) == 4);
109
110 for (int i = 0; i < inst->numSrcRegs(); i++) {
108
109 for (int i = 0; i < inst->numSrcRegs(); i++) {
111 uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size);
110 uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0);
112
111
113 if (isNan(&src_bits, size) ) {
114 if (isSnan(&src_bits, size)) {
115 switch (size)
116 {
117 case 32: mips_nan = MIPS32_QNAN; break;
118 case 64: mips_nan = MIPS64_QNAN; break;
119 default: panic("Unsupported Floating Point Size (%d)", size);
120 }
121 } else {
122 mips_nan = src_bits;
123 }
124
125 xc->setFloatRegOperandBits(inst, 0, mips_nan, size);
112 if (isNan(&src_bits, 32) ) {
113 mips_nan = MIPS32_QNAN;
114 xc->setFloatRegOperandBits(inst, 0, mips_nan);
126 if (traceData) { traceData->setData(mips_nan); }
127 return true;
128 }
129 }
130 return false;
131 }
132
133 template <class T>
134 bool
135 fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
136 Trace::InstRecord *traceData)
137 {
138 uint64_t mips_nan = 0;
139 T src_op = dest_val;
115 if (traceData) { traceData->setData(mips_nan); }
116 return true;
117 }
118 }
119 return false;
120 }
121
122 template <class T>
123 bool
124 fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
125 Trace::InstRecord *traceData)
126 {
127 uint64_t mips_nan = 0;
128 T src_op = dest_val;
140 int size = sizeof(src_op) * 8;
129 assert(sizeof(T) == 4);
141
130
142 if (isNan(&src_op, size)) {
143 switch (size)
144 {
145 case 32: mips_nan = MIPS32_QNAN; break;
146 case 64: mips_nan = MIPS64_QNAN; break;
147 default: panic("Unsupported Floating Point Size (%d)", size);
148 }
131 if (isNan(&src_op, 32)) {
132 mips_nan = MIPS32_QNAN;
149
150 //Set value to QNAN
133
134 //Set value to QNAN
151 cpu->setFloatRegOperandBits(inst, 0, mips_nan, size);
135 cpu->setFloatRegOperandBits(inst, 0, mips_nan);
152
153 //Read FCSR from FloatRegFile
154 uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
155
156 uint32_t new_fcsr = genInvalidVector(fcsr_bits);
157
158 //Write FCSR from FloatRegFile
159 cpu->tcBase()->setFloatRegBits(FCSR, new_fcsr);

--- 227 unchanged lines hidden --- 		136
137 //Read FCSR from FloatRegFile
138 uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
139
140 uint32_t new_fcsr = genInvalidVector(fcsr_bits);
141
142 //Write FCSR from FloatRegFile
143 cpu->tcBase()->setFloatRegBits(FCSR, new_fcsr);

--- 227 unchanged lines hidden ---