fp.isa (2847:6b19f07d9666) fp.isa (3735:86a7cf4dcc11)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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94 fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type,
95 Trace::InstRecord *traceData)
96 {
97 uint64_t mips_nan = 0;
98 T src_op = 0;
99 int size = sizeof(src_op) * 8;
100
101 for (int i = 0; i < inst->numSrcRegs(); i++) {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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94 fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type,
95 Trace::InstRecord *traceData)
96 {
97 uint64_t mips_nan = 0;
98 T src_op = 0;
99 int size = sizeof(src_op) * 8;
100
101 for (int i = 0; i < inst->numSrcRegs(); i++) {
102 uint64_t src_bits = xc->readFloatRegBits(inst, 0, size);
102 uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size);
103
104 if (isNan(&src_bits, size) ) {
105 if (isSnan(&src_bits, size)) {
106 switch (size)
107 {
108 case 32: mips_nan = MIPS32_QNAN; break;
109 case 64: mips_nan = MIPS64_QNAN; break;
110 default: panic("Unsupported Floating Point Size (%d)", size);
111 }
112 } else {
113 mips_nan = src_bits;
114 }
115
103
104 if (isNan(&src_bits, size) ) {
105 if (isSnan(&src_bits, size)) {
106 switch (size)
107 {
108 case 32: mips_nan = MIPS32_QNAN; break;
109 case 64: mips_nan = MIPS64_QNAN; break;
110 default: panic("Unsupported Floating Point Size (%d)", size);
111 }
112 } else {
113 mips_nan = src_bits;
114 }
115
116 xc->setFloatRegBits(inst, 0, mips_nan, size);
116 xc->setFloatRegOperandBits(inst, 0, mips_nan, size);
117 if (traceData) { traceData->setData(mips_nan); }
118 return true;
119 }
120 }
121 return false;
122 }
123
124 template <class T>

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134 switch (size)
135 {
136 case 32: mips_nan = MIPS32_QNAN; break;
137 case 64: mips_nan = MIPS64_QNAN; break;
138 default: panic("Unsupported Floating Point Size (%d)", size);
139 }
140
141 //Set value to QNAN
117 if (traceData) { traceData->setData(mips_nan); }
118 return true;
119 }
120 }
121 return false;
122 }
123
124 template <class T>

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134 switch (size)
135 {
136 case 32: mips_nan = MIPS32_QNAN; break;
137 case 64: mips_nan = MIPS64_QNAN; break;
138 default: panic("Unsupported Floating Point Size (%d)", size);
139 }
140
141 //Set value to QNAN
142 cpu->setFloatRegBits(inst, 0, mips_nan, size);
142 cpu->setFloatRegOperandBits(inst, 0, mips_nan, size);
143
144 //Read FCSR from FloatRegFile
145 uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
146
147 //Write FCSR from FloatRegFile
148 cpu->tcBase()->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
149
150 if (traceData) { traceData->setData(mips_nan); }

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144 //Read FCSR from FloatRegFile
145 uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
146
147 //Write FCSR from FloatRegFile
148 cpu->tcBase()->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
149
150 if (traceData) { traceData->setData(mips_nan); }

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