fp.isa (2754:e3d023bc752c) fp.isa (2847:6b19f07d9666)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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137 case 64: mips_nan = MIPS64_QNAN; break;
138 default: panic("Unsupported Floating Point Size (%d)", size);
139 }
140
141 //Set value to QNAN
142 cpu->setFloatRegBits(inst, 0, mips_nan, size);
143
144 //Read FCSR from FloatRegFile
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 128 unchanged lines hidden (view full) ---

137 case 64: mips_nan = MIPS64_QNAN; break;
138 default: panic("Unsupported Floating Point Size (%d)", size);
139 }
140
141 //Set value to QNAN
142 cpu->setFloatRegBits(inst, 0, mips_nan, size);
143
144 //Read FCSR from FloatRegFile
145 uint32_t fcsr_bits = cpu->tc->readFloatRegBits(FCSR);
145 uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
146
147 //Write FCSR from FloatRegFile
146
147 //Write FCSR from FloatRegFile
148 cpu->tc->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
148 cpu->tcBase()->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
149
150 if (traceData) { traceData->setData(mips_nan); }
151 return true;
152 }
153
154 return false;
155 }
156
157 void
158 fpResetCauseBits(%(CPU_exec_context)s *cpu)
159 {
160 //Read FCSR from FloatRegFile
149
150 if (traceData) { traceData->setData(mips_nan); }
151 return true;
152 }
153
154 return false;
155 }
156
157 void
158 fpResetCauseBits(%(CPU_exec_context)s *cpu)
159 {
160 //Read FCSR from FloatRegFile
161 uint32_t fcsr = cpu->tc->readFloatRegBits(FCSR);
161 uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR);
162
163 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
164
165 //Write FCSR from FloatRegFile
162
163 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
164
165 //Write FCSR from FloatRegFile
166 cpu->tc->setFloatRegBits(FCSR, fcsr);
166 cpu->tcBase()->setFloatRegBits(FCSR, fcsr);
167 }
168}};
169
170def template FloatingPointExecute {{
171 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
172 {
173 Fault fault = NoFault;
174
175 %(fp_enable_check)s;
176
177 //When is the right time to reset cause bits?
178 //start of every instruction or every cycle?
167 }
168}};
169
170def template FloatingPointExecute {{
171 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
172 {
173 Fault fault = NoFault;
174
175 %(fp_enable_check)s;
176
177 //When is the right time to reset cause bits?
178 //start of every instruction or every cycle?
179#if FULL_SYSTEM
179 fpResetCauseBits(xc);
180 fpResetCauseBits(xc);
180
181#endif
181 %(op_decl)s;
182 %(op_rd)s;
183
184 //Check if any FP operand is a NaN value
185 if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) {
186 %(code)s;
187
188 //Change this code for Full-System/Sycall Emulation
189 //separation
190 //----
191 //Should Full System-Mode throw a fault here?
192 //----
193 //Check for IEEE 754 FP Exceptions
194 //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
182 %(op_decl)s;
183 %(op_rd)s;
184
185 //Check if any FP operand is a NaN value
186 if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) {
187 %(code)s;
188
189 //Change this code for Full-System/Sycall Emulation
190 //separation
191 //----
192 //Should Full System-Mode throw a fault here?
193 //----
194 //Check for IEEE 754 FP Exceptions
195 //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
195 if (!fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
196 if (
197#if FULL_SYSTEM
198 !fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
199#endif
196 fault == NoFault)
197 {
198 %(op_wb)s;
199 }
200 }
201
202 return fault;
203 }

--- 166 unchanged lines hidden --- 		200 fault == NoFault)
201 {
202 %(op_wb)s;
203 }
204 }
205
206 return fault;
207 }

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