fp.isa (2686:f0d591379ac3) fp.isa (2687:9721a59675b8)
1// -*- mode:c++ -*-
2
3////////////////////////////////////////////////////////////////////
4//
5// Floating Point operate instructions
6//
7
8output header {{

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90 return true;
91 }
92 }
93 return false;
94 }
95
96 template <class T>
97 bool
1// -*- mode:c++ -*-
2
3////////////////////////////////////////////////////////////////////
4//
5// Floating Point operate instructions
6//
7
8output header {{

--- 81 unchanged lines hidden (view full) ---

90 return true;
91 }
92 }
93 return false;
94 }
95
96 template <class T>
97 bool
98 fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *xc, const T dest_val,
98 fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
99 Trace::InstRecord *traceData)
100 {
101 uint64_t mips_nan = 0;
102 T src_op = dest_val;
103 int size = sizeof(src_op) * 8;
104
105 if (isNan(&src_op, size)) {
106 switch (size)
107 {
108 case 32: mips_nan = MIPS32_QNAN; break;
109 case 64: mips_nan = MIPS64_QNAN; break;
110 default: panic("Unsupported Floating Point Size (%d)", size);
111 }
112
113 //Set value to QNAN
99 Trace::InstRecord *traceData)
100 {
101 uint64_t mips_nan = 0;
102 T src_op = dest_val;
103 int size = sizeof(src_op) * 8;
104
105 if (isNan(&src_op, size)) {
106 switch (size)
107 {
108 case 32: mips_nan = MIPS32_QNAN; break;
109 case 64: mips_nan = MIPS64_QNAN; break;
110 default: panic("Unsupported Floating Point Size (%d)", size);
111 }
112
113 //Set value to QNAN
114 xc->setFloatRegBits(inst, 0, mips_nan, size);
114 cpu->setFloatRegBits(inst, 0, mips_nan, size);
115
116 //Read FCSR from FloatRegFile
115
116 //Read FCSR from FloatRegFile
117 uint32_t fcsr_bits = xc->cpuXC->readFloatRegBits(FCSR);
117 uint32_t fcsr_bits = cpu->tc->readFloatRegBits(FCSR);
118
119 //Write FCSR from FloatRegFile
118
119 //Write FCSR from FloatRegFile
120 xc->cpuXC->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
120 cpu->tc->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
121
122 if (traceData) { traceData->setData(mips_nan); }
123 return true;
124 }
125
126 return false;
127 }
128
129 void
121
122 if (traceData) { traceData->setData(mips_nan); }
123 return true;
124 }
125
126 return false;
127 }
128
129 void
130 fpResetCauseBits(%(CPU_exec_context)s *xc)
130 fpResetCauseBits(%(CPU_exec_context)s *cpu)
131 {
132 //Read FCSR from FloatRegFile
131 {
132 //Read FCSR from FloatRegFile
133 uint32_t fcsr = xc->cpuXC->readFloatRegBits(FCSR);
133 uint32_t fcsr = cpu->tc->readFloatRegBits(FCSR);
134
135 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
136
137 //Write FCSR from FloatRegFile
134
135 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
136
137 //Write FCSR from FloatRegFile
138 xc->cpuXC->setFloatRegBits(FCSR, fcsr);
138 cpu->tc->setFloatRegBits(FCSR, fcsr);
139 }
140}};
141
142def template FloatingPointExecute {{
143 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
144 {
145 Fault fault = NoFault;
146

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140}};
141
142def template FloatingPointExecute {{
143 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
144 {
145 Fault fault = NoFault;
146

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