fp.isa (12616:4b463b4dc098) fp.isa (13611:c8b7847b4171)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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134 if (isNan(&src_op, 32)) {
135 mips_nan = MIPS32_QNAN;
136
137 //Set value to QNAN
138 cpu->setFloatRegOperandBits(inst, 0, mips_nan);
139
140 //Read FCSR from FloatRegFile
141 uint32_t fcsr_bits =
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 125 unchanged lines hidden (view full) ---

134 if (isNan(&src_op, 32)) {
135 mips_nan = MIPS32_QNAN;
136
137 //Set value to QNAN
138 cpu->setFloatRegOperandBits(inst, 0, mips_nan);
139
140 //Read FCSR from FloatRegFile
141 uint32_t fcsr_bits =
142 cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
142 cpu->tcBase()->readFloatReg(FLOATREG_FCSR);
143
144 uint32_t new_fcsr = genInvalidVector(fcsr_bits);
145
146 //Write FCSR from FloatRegFile
143
144 uint32_t new_fcsr = genInvalidVector(fcsr_bits);
145
146 //Write FCSR from FloatRegFile
147 cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, new_fcsr);
147 cpu->tcBase()->setFloatReg(FLOATREG_FCSR, new_fcsr);
148
149 if (traceData) { traceData->setData(mips_nan); }
150 return true;
151 }
152
153 return false;
154 }
155
156 void
157 fpResetCauseBits(ExecContext *cpu)
158 {
159 //Read FCSR from FloatRegFile
148
149 if (traceData) { traceData->setData(mips_nan); }
150 return true;
151 }
152
153 return false;
154 }
155
156 void
157 fpResetCauseBits(ExecContext *cpu)
158 {
159 //Read FCSR from FloatRegFile
160 uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
160 uint32_t fcsr = cpu->tcBase()->readFloatReg(FLOATREG_FCSR);
161
162 // TODO: Use utility function here
163 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
164
165 //Write FCSR from FloatRegFile
161
162 // TODO: Use utility function here
163 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
164
165 //Write FCSR from FloatRegFile
166 cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr);
166 cpu->tcBase()->setFloatReg(FLOATREG_FCSR, fcsr);
167 }
168}};
169
170def template FloatingPointExecute {{
171 Fault %(class_name)s::execute(
172 ExecContext *xc, Trace::InstRecord *traceData) const
173 {
174 Fault fault = NoFault;

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168}};
169
170def template FloatingPointExecute {{
171 Fault %(class_name)s::execute(
172 ExecContext *xc, Trace::InstRecord *traceData) const
173 {
174 Fault fault = NoFault;

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