1// -*- mode:c++ -*-
2
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3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
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| 3// Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved |
4
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5// This software is part of the M5 simulator.
6
7// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
8// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
9// TO THESE TERMS AND CONDITIONS.
10
11// Permission is granted to use, copy, create derivative works and
12// distribute this software and such derivative works for any purpose,
13// so long as (1) the copyright notice above, this grant of permission,
14// and the disclaimer below appear in all copies and derivative works
15// made, (2) the copyright notice above is augmented as appropriate to
16// reflect the addition of any new copyrightable work in a derivative
17// work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
18// the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
19// advertising or publicity pertaining to the use or distribution of
20// this software without specific, written prior authorization.
21
22// THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND
23// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
24// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
26// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
27// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
28// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
29// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
30// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
31// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
32// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
33// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
34
35//Authors: Korey L. Sewell
36 |
37////////////////////////////////////////////////////////////////////
38//
39// Floating Point operate instructions
40//
41
42output header {{
43 /**
44 * Base class for FP operations.
45 */
46 class FPOp : public MipsStaticInst
47 {
48 protected:
49
50 /// Constructor
51 FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
52 {
53 }
54
55 //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
56
57 //needs function to check for fpEnable or not
58 };
59
60 class FPCompareOp : public FPOp
61 {
62 protected:
63 FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass)
64 {
65 }
66
67 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
68
69 };
70}};
71
72output decoder {{
73 std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
74 {
75 std::stringstream ss;
76
77 ccprintf(ss, "%-10s ", mnemonic);
78
79 ccprintf(ss,"%d",CC);
80
81 if(_numSrcRegs > 0) {
82 ss << ", ";
83 printReg(ss, _srcRegIdx[0]);
84 }
85
86 if(_numSrcRegs > 1) {
87 ss << ", ";
88 printReg(ss, _srcRegIdx[1]);
89 }
90
91 return ss.str();
92 }
93}};
94
95output exec {{
96 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
97 {
98 //@TODO: Implement correct CP0 checks to see if the CP1
99 // unit is enable or not
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94 return NoFault;
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100 if (!isCoprocessorEnabled(xc, 1))
101 return new CoprocessorUnusableFault(1);
102
103 return NoFault; |
104 }
105
106 //If any operand is Nan return the appropriate QNaN
107 template <class T>
108 bool
109 fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type,
110 Trace::InstRecord *traceData)
111 {
112 uint64_t mips_nan = 0;
113 T src_op = 0;
114 int size = sizeof(src_op) * 8;
115
116 for (int i = 0; i < inst->numSrcRegs(); i++) {
117 uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size);
118
119 if (isNan(&src_bits, size) ) {
120 if (isSnan(&src_bits, size)) {
121 switch (size)
122 {
123 case 32: mips_nan = MIPS32_QNAN; break;
124 case 64: mips_nan = MIPS64_QNAN; break;
125 default: panic("Unsupported Floating Point Size (%d)", size);
126 }
127 } else {
128 mips_nan = src_bits;
129 }
130
131 xc->setFloatRegOperandBits(inst, 0, mips_nan, size);
132 if (traceData) { traceData->setData(mips_nan); }
133 return true;
134 }
135 }
136 return false;
137 }
138
139 template <class T>
140 bool
141 fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
142 Trace::InstRecord *traceData)
143 {
144 uint64_t mips_nan = 0;
145 T src_op = dest_val;
146 int size = sizeof(src_op) * 8;
147
148 if (isNan(&src_op, size)) {
149 switch (size)
150 {
151 case 32: mips_nan = MIPS32_QNAN; break;
152 case 64: mips_nan = MIPS64_QNAN; break;
153 default: panic("Unsupported Floating Point Size (%d)", size);
154 }
155
156 //Set value to QNAN
157 cpu->setFloatRegOperandBits(inst, 0, mips_nan, size);
158
159 //Read FCSR from FloatRegFile
160 uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
161
162 uint32_t new_fcsr = genInvalidVector(fcsr_bits);
163
164 //Write FCSR from FloatRegFile
165 cpu->tcBase()->setFloatRegBits(FCSR, new_fcsr);
166
167 if (traceData) { traceData->setData(mips_nan); }
168 return true;
169 }
170
171 return false;
172 }
173
174 void
175 fpResetCauseBits(%(CPU_exec_context)s *cpu)
176 {
177 //Read FCSR from FloatRegFile
178 uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR);
179
180 // TODO: Use utility function here
181 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
182
183 //Write FCSR from FloatRegFile
184 cpu->tcBase()->setFloatRegBits(FCSR, fcsr);
185 }
186}};
187
188def template FloatingPointExecute {{
189 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
190 {
191 Fault fault = NoFault;
192
193 %(fp_enable_check)s;
194
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| 195 |
196 //When is the right time to reset cause bits?
197 //start of every instruction or every cycle?
198#if FULL_SYSTEM
199 fpResetCauseBits(xc);
200#endif
201 %(op_decl)s;
202 %(op_rd)s;
203
204 //Check if any FP operand is a NaN value
205 if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) {
206 %(code)s;
207
208 //Change this code for Full-System/Sycall Emulation
209 //separation
210 //----
211 //Should Full System-Mode throw a fault here?
212 //----
213 //Check for IEEE 754 FP Exceptions
214 //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
215 if (
216#if FULL_SYSTEM
217 !fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
218#endif
219 fault == NoFault)
220 {
221 %(op_wb)s;
222 }
223 }
224
225 return fault;
226 }
227}};
228
229// Primary format for float point operate instructions:
230def format FloatOp(code, *flags) {{
231 iop = InstObjParams(name, Name, 'FPOp', code, flags)
232 header_output = BasicDeclare.subst(iop)
233 decoder_output = BasicConstructor.subst(iop)
234 decode_block = BasicDecode.subst(iop)
235 exec_output = FloatingPointExecute.subst(iop)
236}};
237
238def format FloatCompareOp(cond_code, *flags) {{
239 import sys
240
241 code = 'bool cond;\n'
242 if '.sf' in cond_code or 'SinglePrecision' in flags:
243 if 'QnanException' in flags:
244 code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n'
245 code += '\tFCSR = genInvalidVector(FCSR);\n'
246 code += '\treturn NoFault;'
247 code += '}\n else '
248 code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n'
249 elif '.df' in cond_code or 'DoublePrecision' in flags:
250 if 'QnanException' in flags:
251 code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n'
252 code += '\tFCSR = genInvalidVector(FCSR);\n'
253 code += '\treturn NoFault;'
254 code += '}\n else '
255 code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n'
256 else:
257 sys.exit('Decoder Failed: Can\'t Determine Operand Type\n')
258
259 if 'UnorderedTrue' in flags:
260 code += 'cond = 1;\n'
261 elif 'UnorderedFalse' in flags:
262 code += 'cond = 0;\n'
263 else:
264 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
265
266 code += '} else {\n'
267 code += cond_code + '}'
268 code += 'FCSR = genCCVector(FCSR, CC, cond);\n'
269
270 iop = InstObjParams(name, Name, 'FPCompareOp', code)
271 header_output = BasicDeclare.subst(iop)
272 decoder_output = BasicConstructor.subst(iop)
273 decode_block = BasicDecode.subst(iop)
274 exec_output = BasicExecute.subst(iop)
275}};
276
277def format FloatConvertOp(code, *flags) {{
278 import sys
279
280 #Determine Source Type
281 convert = 'fpConvert('
282 if '.sf' in code:
283 code = 'float ' + code + '\n'
284 convert += 'SINGLE_TO_'
285 elif '.df' in code:
286 code = 'double ' + code + '\n'
287 convert += 'DOUBLE_TO_'
288 elif '.uw' in code:
289 code = 'uint32_t ' + code + '\n'
290 convert += 'WORD_TO_'
291 elif '.ud' in code:
292 code = 'uint64_t ' + code + '\n'
293 convert += 'LONG_TO_'
294 else:
295 sys.exit("Error Determining Source Type for Conversion")
296
297 #Determine Destination Type
298 if 'ToSingle' in flags:
299 code += 'Fd.uw = ' + convert + 'SINGLE, '
300 elif 'ToDouble' in flags:
301 code += 'Fd.ud = ' + convert + 'DOUBLE, '
302 elif 'ToWord' in flags:
303 code += 'Fd.uw = ' + convert + 'WORD, '
304 elif 'ToLong' in flags:
305 code += 'Fd.ud = ' + convert + 'LONG, '
306 else:
307 sys.exit("Error Determining Destination Type for Conversion")
308
309 #Figure out how to round value
310 if 'Ceil' in flags:
311 code += 'ceil(val)); '
312 elif 'Floor' in flags:
313 code += 'floor(val)); '
314 elif 'Round' in flags:
315 code += 'roundFP(val, 0)); '
316 elif 'Trunc' in flags:
317 code += 'truncFP(val));'
318 else:
319 code += 'val); '
320
321 iop = InstObjParams(name, Name, 'FPOp', code)
322 header_output = BasicDeclare.subst(iop)
323 decoder_output = BasicConstructor.subst(iop)
324 decode_block = BasicDecode.subst(iop)
325 exec_output = BasicExecute.subst(iop)
326}};
327
328def format FloatAccOp(code, *flags) {{
329 iop = InstObjParams(name, Name, 'FPOp', code, flags)
330 header_output = BasicDeclare.subst(iop)
331 decoder_output = BasicConstructor.subst(iop)
332 decode_block = BasicDecode.subst(iop)
333 exec_output = BasicExecute.subst(iop)
334}};
335
336// Primary format for float64 operate instructions:
337def format Float64Op(code, *flags) {{
338 iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
339 header_output = BasicDeclare.subst(iop)
340 decoder_output = BasicConstructor.subst(iop)
341 decode_block = BasicDecode.subst(iop)
342 exec_output = BasicExecute.subst(iop)
343}};
344
345def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
346 import sys
347
348 code = 'bool cond1, cond2;\n'
349 code += 'bool code_block1, code_block2;\n'
350 code += 'code_block1 = code_block2 = true;\n'
351
352 if 'QnanException' in flags:
353 code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n'
354 code += '\tFCSR = genInvalidVector(FCSR);\n'
355 code += 'code_block1 = false;'
356 code += '}\n'
357 code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n'
358 code += '\tFCSR = genInvalidVector(FCSR);\n'
359 code += 'code_block2 = false;'
360 code += '}\n'
361
362 code += 'if (code_block1) {'
363 code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n'
364 if 'UnorderedTrue' in flags:
365 code += 'cond1 = 1;\n'
366 elif 'UnorderedFalse' in flags:
367 code += 'cond1 = 0;\n'
368 else:
369 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
370 code += '} else {\n'
371 code += cond_code1
372 code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n'
373
374 code += 'if (code_block2) {'
375 code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n'
376 if 'UnorderedTrue' in flags:
377 code += 'cond2 = 1;\n'
378 elif 'UnorderedFalse' in flags:
379 code += 'cond2 = 0;\n'
380 else:
381 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
382 code += '} else {\n'
383 code += cond_code2
384 code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}'
385
386 iop = InstObjParams(name, Name, 'FPCompareOp', code)
387 header_output = BasicDeclare.subst(iop)
388 decoder_output = BasicConstructor.subst(iop)
389 decode_block = BasicDecode.subst(iop)
390 exec_output = BasicExecute.subst(iop)
391}};
392
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