1// -*- mode:c++ -*- 2 3// Copyright (c) 2006 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 73 unchanged lines hidden (view full) --- 82 printReg(ss, _srcRegIdx[1]); 83 } 84 85 return ss.str(); 86 } 87}}; 88 89output exec {{ |
90 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) 91 { 92 //@TODO: Implement correct CP0 checks to see if the CP1 93 // unit is enable or not 94 return NoFault; 95 } |
96 97 //If any operand is Nan return the appropriate QNaN 98 template <class T> 99 bool 100 fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type, 101 Trace::InstRecord *traceData) 102 { 103 uint64_t mips_nan = 0; --- 42 unchanged lines hidden (view full) --- 146 147 //Set value to QNAN 148 cpu->setFloatRegOperandBits(inst, 0, mips_nan, size); 149 150 //Read FCSR from FloatRegFile 151 uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR); 152 153 //Write FCSR from FloatRegFile |
154 cpu->tcBase()->setFloatRegOperandBits(FCSR, genInvalidVector(fcsr_bits)); |
155 156 if (traceData) { traceData->setData(mips_nan); } 157 return true; 158 } 159 160 return false; 161 } 162 163 void 164 fpResetCauseBits(%(CPU_exec_context)s *cpu) 165 { 166 //Read FCSR from FloatRegFile 167 uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR); 168 |
169 // TODO: Use utility function here |
170 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); 171 172 //Write FCSR from FloatRegFile 173 cpu->tcBase()->setFloatRegBits(FCSR, fcsr); 174 } 175}}; 176 177def template FloatingPointExecute {{ --- 203 unchanged lines hidden --- |