1// -*- mode:c++ -*-
2
3////////////////////////////////////////////////////////////////////
4//
5// Floating Point operate instructions
6//
7
8output header {{
9 /**
10 * Base class for FP operations.
11 */
12 class FPOp : public MipsStaticInst
13 {
14 protected:
15
16 /// Constructor
17 FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
18 {
19 }
20
21 //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
22
23 //needs function to check for fpEnable or not
24 };
25
26 class FPCompareOp : public FPOp
27 {
28 protected:
29 FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass)
30 {
31 }
32
33 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
34
35 };
36}};
37
38output decoder {{
39 std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
40 {
41 std::stringstream ss;
42
43 ccprintf(ss, "%-10s ", mnemonic);
44
45 ccprintf(ss,"%d",CC);
46
47 if(_numSrcRegs > 0) {
48 ss << ", ";
49 printReg(ss, _srcRegIdx[0]);
50 }
51
52 if(_numSrcRegs > 1) {
53 ss << ", ";
54 printReg(ss, _srcRegIdx[1]);
55 }
56
57 return ss.str();
58 }
59}};
60
61output exec {{
62
63 //If any operand is Nan return the appropriate QNaN
64 template <class T>
65 bool
66 fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type,
67 Trace::InstRecord *traceData)
68 {
69 uint64_t mips_nan = 0;
70 T src_op = 0;
71 int size = sizeof(src_op) * 8;
72
73 for (int i = 0; i < inst->numSrcRegs(); i++) {
74 uint64_t src_bits = xc->readFloatRegBits(inst, 0, size);
75
76 if (isNan(&src_bits, size) ) {
77 if (isSnan(&src_bits, size)) {
78 switch (size)
79 {
80 case 32: mips_nan = MIPS32_QNAN; break;
81 case 64: mips_nan = MIPS64_QNAN; break;
82 default: panic("Unsupported Floating Point Size (%d)", size);
83 }
84 } else {
85 mips_nan = src_bits;
86 }
87
88 xc->setFloatRegBits(inst, 0, mips_nan, size);
89 if (traceData) { traceData->setData(mips_nan); }
90 return true;
91 }
92 }
93 return false;
94 }
95
96 template <class T>
97 bool
| 1// -*- mode:c++ -*-
2
3////////////////////////////////////////////////////////////////////
4//
5// Floating Point operate instructions
6//
7
8output header {{
9 /**
10 * Base class for FP operations.
11 */
12 class FPOp : public MipsStaticInst
13 {
14 protected:
15
16 /// Constructor
17 FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
18 {
19 }
20
21 //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
22
23 //needs function to check for fpEnable or not
24 };
25
26 class FPCompareOp : public FPOp
27 {
28 protected:
29 FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass)
30 {
31 }
32
33 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
34
35 };
36}};
37
38output decoder {{
39 std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
40 {
41 std::stringstream ss;
42
43 ccprintf(ss, "%-10s ", mnemonic);
44
45 ccprintf(ss,"%d",CC);
46
47 if(_numSrcRegs > 0) {
48 ss << ", ";
49 printReg(ss, _srcRegIdx[0]);
50 }
51
52 if(_numSrcRegs > 1) {
53 ss << ", ";
54 printReg(ss, _srcRegIdx[1]);
55 }
56
57 return ss.str();
58 }
59}};
60
61output exec {{
62
63 //If any operand is Nan return the appropriate QNaN
64 template <class T>
65 bool
66 fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type,
67 Trace::InstRecord *traceData)
68 {
69 uint64_t mips_nan = 0;
70 T src_op = 0;
71 int size = sizeof(src_op) * 8;
72
73 for (int i = 0; i < inst->numSrcRegs(); i++) {
74 uint64_t src_bits = xc->readFloatRegBits(inst, 0, size);
75
76 if (isNan(&src_bits, size) ) {
77 if (isSnan(&src_bits, size)) {
78 switch (size)
79 {
80 case 32: mips_nan = MIPS32_QNAN; break;
81 case 64: mips_nan = MIPS64_QNAN; break;
82 default: panic("Unsupported Floating Point Size (%d)", size);
83 }
84 } else {
85 mips_nan = src_bits;
86 }
87
88 xc->setFloatRegBits(inst, 0, mips_nan, size);
89 if (traceData) { traceData->setData(mips_nan); }
90 return true;
91 }
92 }
93 return false;
94 }
95
96 template <class T>
97 bool
|
98 fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *xc, const T dest_val,
| 98 fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
|
99 Trace::InstRecord *traceData)
100 {
101 uint64_t mips_nan = 0;
102 T src_op = dest_val;
103 int size = sizeof(src_op) * 8;
104
105 if (isNan(&src_op, size)) {
106 switch (size)
107 {
108 case 32: mips_nan = MIPS32_QNAN; break;
109 case 64: mips_nan = MIPS64_QNAN; break;
110 default: panic("Unsupported Floating Point Size (%d)", size);
111 }
112
113 //Set value to QNAN
| 99 Trace::InstRecord *traceData)
100 {
101 uint64_t mips_nan = 0;
102 T src_op = dest_val;
103 int size = sizeof(src_op) * 8;
104
105 if (isNan(&src_op, size)) {
106 switch (size)
107 {
108 case 32: mips_nan = MIPS32_QNAN; break;
109 case 64: mips_nan = MIPS64_QNAN; break;
110 default: panic("Unsupported Floating Point Size (%d)", size);
111 }
112
113 //Set value to QNAN
|
114 xc->setFloatRegBits(inst, 0, mips_nan, size);
| 114 cpu->setFloatRegBits(inst, 0, mips_nan, size);
|
115
116 //Read FCSR from FloatRegFile
| 115
116 //Read FCSR from FloatRegFile
|
117 uint32_t fcsr_bits = xc->cpuXC->readFloatRegBits(FCSR);
| 117 uint32_t fcsr_bits = cpu->tc->readFloatRegBits(FCSR);
|
118
119 //Write FCSR from FloatRegFile
| 118
119 //Write FCSR from FloatRegFile
|
120 xc->cpuXC->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
| 120 cpu->tc->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
|
121
122 if (traceData) { traceData->setData(mips_nan); }
123 return true;
124 }
125
126 return false;
127 }
128
129 void
| 121
122 if (traceData) { traceData->setData(mips_nan); }
123 return true;
124 }
125
126 return false;
127 }
128
129 void
|
130 fpResetCauseBits(%(CPU_exec_context)s *xc)
| 130 fpResetCauseBits(%(CPU_exec_context)s *cpu)
|
131 {
132 //Read FCSR from FloatRegFile
| 131 {
132 //Read FCSR from FloatRegFile
|
133 uint32_t fcsr = xc->cpuXC->readFloatRegBits(FCSR);
| 133 uint32_t fcsr = cpu->tc->readFloatRegBits(FCSR);
|
134
135 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
136
137 //Write FCSR from FloatRegFile
| 134
135 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
136
137 //Write FCSR from FloatRegFile
|
138 xc->cpuXC->setFloatRegBits(FCSR, fcsr);
| 138 cpu->tc->setFloatRegBits(FCSR, fcsr);
|
139 }
140}};
141
142def template FloatingPointExecute {{
143 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
144 {
145 Fault fault = NoFault;
146
147 %(fp_enable_check)s;
148
149 //When is the right time to reset cause bits?
150 //start of every instruction or every cycle?
151 fpResetCauseBits(xc);
152
153 %(op_decl)s;
154 %(op_rd)s;
155
156 //Check if any FP operand is a NaN value
157 if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) {
158 %(code)s;
159
160 //Change this code for Full-System/Sycall Emulation
161 //separation
162 //----
163 //Should Full System-Mode throw a fault here?
164 //----
165 //Check for IEEE 754 FP Exceptions
166 //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
167 if (!fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
168 fault == NoFault)
169 {
170 %(op_wb)s;
171 }
172 }
173
174 return fault;
175 }
176}};
177
178// Primary format for float point operate instructions:
179def format FloatOp(code, *flags) {{
180 iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags)
181 header_output = BasicDeclare.subst(iop)
182 decoder_output = BasicConstructor.subst(iop)
183 decode_block = BasicDecode.subst(iop)
184 exec_output = FloatingPointExecute.subst(iop)
185}};
186
187def format FloatCompareOp(cond_code, *flags) {{
188 import sys
189
190 code = 'bool cond;\n'
191 if '.sf' in cond_code or 'SinglePrecision' in flags:
192 if 'QnanException' in flags:
193 code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n'
194 code += '\tFCSR = genInvalidVector(FCSR);\n'
195 code += '\treturn NoFault;'
196 code += '}\n else '
197 code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n'
198 elif '.df' in cond_code or 'DoublePrecision' in flags:
199 if 'QnanException' in flags:
200 code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n'
201 code += '\tFCSR = genInvalidVector(FCSR);\n'
202 code += '\treturn NoFault;'
203 code += '}\n else '
204 code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n'
205 else:
206 sys.exit('Decoder Failed: Can\'t Determine Operand Type\n')
207
208 if 'UnorderedTrue' in flags:
209 code += 'cond = 1;\n'
210 elif 'UnorderedFalse' in flags:
211 code += 'cond = 0;\n'
212 else:
213 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
214
215 code += '} else {\n'
216 code += cond_code + '}'
217 code += 'FCSR = genCCVector(FCSR, CC, cond);\n'
218
219 iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code))
220 header_output = BasicDeclare.subst(iop)
221 decoder_output = BasicConstructor.subst(iop)
222 decode_block = BasicDecode.subst(iop)
223 exec_output = BasicExecute.subst(iop)
224}};
225
226def format FloatConvertOp(code, *flags) {{
227 import sys
228
229 #Determine Source Type
230 convert = 'fpConvert('
231 if '.sf' in code:
232 code = 'float ' + code + '\n'
233 convert += 'SINGLE_TO_'
234 elif '.df' in code:
235 code = 'double ' + code + '\n'
236 convert += 'DOUBLE_TO_'
237 elif '.uw' in code:
238 code = 'uint32_t ' + code + '\n'
239 convert += 'WORD_TO_'
240 elif '.ud' in code:
241 code = 'uint64_t ' + code + '\n'
242 convert += 'LONG_TO_'
243 else:
244 sys.exit("Error Determining Source Type for Conversion")
245
246 #Determine Destination Type
247 if 'ToSingle' in flags:
248 code += 'Fd.uw = ' + convert + 'SINGLE, '
249 elif 'ToDouble' in flags:
250 code += 'Fd.ud = ' + convert + 'DOUBLE, '
251 elif 'ToWord' in flags:
252 code += 'Fd.uw = ' + convert + 'WORD, '
253 elif 'ToLong' in flags:
254 code += 'Fd.ud = ' + convert + 'LONG, '
255 else:
256 sys.exit("Error Determining Destination Type for Conversion")
257
258 #Figure out how to round value
259 if 'Ceil' in flags:
260 code += 'ceil(val)); '
261 elif 'Floor' in flags:
262 code += 'floor(val)); '
263 elif 'Round' in flags:
264 code += 'roundFP(val, 0)); '
265 elif 'Trunc' in flags:
266 code += 'truncFP(val));'
267 else:
268 code += 'val); '
269
270 iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code))
271 header_output = BasicDeclare.subst(iop)
272 decoder_output = BasicConstructor.subst(iop)
273 decode_block = BasicDecode.subst(iop)
274 exec_output = BasicExecute.subst(iop)
275}};
276
277def format FloatAccOp(code, *flags) {{
278 iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags)
279 header_output = BasicDeclare.subst(iop)
280 decoder_output = BasicConstructor.subst(iop)
281 decode_block = BasicDecode.subst(iop)
282 exec_output = BasicExecute.subst(iop)
283}};
284
285// Primary format for float64 operate instructions:
286def format Float64Op(code, *flags) {{
287 iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
288 header_output = BasicDeclare.subst(iop)
289 decoder_output = BasicConstructor.subst(iop)
290 decode_block = BasicDecode.subst(iop)
291 exec_output = BasicExecute.subst(iop)
292}};
293
294def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
295 import sys
296
297 code = 'bool cond1, cond2;\n'
298 code += 'bool code_block1, code_block2;\n'
299 code += 'code_block1 = code_block2 = true;\n'
300
301 if 'QnanException' in flags:
302 code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n'
303 code += '\tFCSR = genInvalidVector(FCSR);\n'
304 code += 'code_block1 = false;'
305 code += '}\n'
306 code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n'
307 code += '\tFCSR = genInvalidVector(FCSR);\n'
308 code += 'code_block2 = false;'
309 code += '}\n'
310
311 code += 'if (code_block1) {'
312 code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n'
313 if 'UnorderedTrue' in flags:
314 code += 'cond1 = 1;\n'
315 elif 'UnorderedFalse' in flags:
316 code += 'cond1 = 0;\n'
317 else:
318 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
319 code += '} else {\n'
320 code += cond_code1
321 code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n'
322
323 code += 'if (code_block2) {'
324 code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n'
325 if 'UnorderedTrue' in flags:
326 code += 'cond2 = 1;\n'
327 elif 'UnorderedFalse' in flags:
328 code += 'cond2 = 0;\n'
329 else:
330 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
331 code += '} else {\n'
332 code += cond_code2
333 code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}'
334
335 iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code))
336 header_output = BasicDeclare.subst(iop)
337 decoder_output = BasicConstructor.subst(iop)
338 decode_block = BasicDecode.subst(iop)
339 exec_output = BasicExecute.subst(iop)
340}};
341
| 139 }
140}};
141
142def template FloatingPointExecute {{
143 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
144 {
145 Fault fault = NoFault;
146
147 %(fp_enable_check)s;
148
149 //When is the right time to reset cause bits?
150 //start of every instruction or every cycle?
151 fpResetCauseBits(xc);
152
153 %(op_decl)s;
154 %(op_rd)s;
155
156 //Check if any FP operand is a NaN value
157 if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) {
158 %(code)s;
159
160 //Change this code for Full-System/Sycall Emulation
161 //separation
162 //----
163 //Should Full System-Mode throw a fault here?
164 //----
165 //Check for IEEE 754 FP Exceptions
166 //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
167 if (!fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
168 fault == NoFault)
169 {
170 %(op_wb)s;
171 }
172 }
173
174 return fault;
175 }
176}};
177
178// Primary format for float point operate instructions:
179def format FloatOp(code, *flags) {{
180 iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags)
181 header_output = BasicDeclare.subst(iop)
182 decoder_output = BasicConstructor.subst(iop)
183 decode_block = BasicDecode.subst(iop)
184 exec_output = FloatingPointExecute.subst(iop)
185}};
186
187def format FloatCompareOp(cond_code, *flags) {{
188 import sys
189
190 code = 'bool cond;\n'
191 if '.sf' in cond_code or 'SinglePrecision' in flags:
192 if 'QnanException' in flags:
193 code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n'
194 code += '\tFCSR = genInvalidVector(FCSR);\n'
195 code += '\treturn NoFault;'
196 code += '}\n else '
197 code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n'
198 elif '.df' in cond_code or 'DoublePrecision' in flags:
199 if 'QnanException' in flags:
200 code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n'
201 code += '\tFCSR = genInvalidVector(FCSR);\n'
202 code += '\treturn NoFault;'
203 code += '}\n else '
204 code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n'
205 else:
206 sys.exit('Decoder Failed: Can\'t Determine Operand Type\n')
207
208 if 'UnorderedTrue' in flags:
209 code += 'cond = 1;\n'
210 elif 'UnorderedFalse' in flags:
211 code += 'cond = 0;\n'
212 else:
213 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
214
215 code += '} else {\n'
216 code += cond_code + '}'
217 code += 'FCSR = genCCVector(FCSR, CC, cond);\n'
218
219 iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code))
220 header_output = BasicDeclare.subst(iop)
221 decoder_output = BasicConstructor.subst(iop)
222 decode_block = BasicDecode.subst(iop)
223 exec_output = BasicExecute.subst(iop)
224}};
225
226def format FloatConvertOp(code, *flags) {{
227 import sys
228
229 #Determine Source Type
230 convert = 'fpConvert('
231 if '.sf' in code:
232 code = 'float ' + code + '\n'
233 convert += 'SINGLE_TO_'
234 elif '.df' in code:
235 code = 'double ' + code + '\n'
236 convert += 'DOUBLE_TO_'
237 elif '.uw' in code:
238 code = 'uint32_t ' + code + '\n'
239 convert += 'WORD_TO_'
240 elif '.ud' in code:
241 code = 'uint64_t ' + code + '\n'
242 convert += 'LONG_TO_'
243 else:
244 sys.exit("Error Determining Source Type for Conversion")
245
246 #Determine Destination Type
247 if 'ToSingle' in flags:
248 code += 'Fd.uw = ' + convert + 'SINGLE, '
249 elif 'ToDouble' in flags:
250 code += 'Fd.ud = ' + convert + 'DOUBLE, '
251 elif 'ToWord' in flags:
252 code += 'Fd.uw = ' + convert + 'WORD, '
253 elif 'ToLong' in flags:
254 code += 'Fd.ud = ' + convert + 'LONG, '
255 else:
256 sys.exit("Error Determining Destination Type for Conversion")
257
258 #Figure out how to round value
259 if 'Ceil' in flags:
260 code += 'ceil(val)); '
261 elif 'Floor' in flags:
262 code += 'floor(val)); '
263 elif 'Round' in flags:
264 code += 'roundFP(val, 0)); '
265 elif 'Trunc' in flags:
266 code += 'truncFP(val));'
267 else:
268 code += 'val); '
269
270 iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code))
271 header_output = BasicDeclare.subst(iop)
272 decoder_output = BasicConstructor.subst(iop)
273 decode_block = BasicDecode.subst(iop)
274 exec_output = BasicExecute.subst(iop)
275}};
276
277def format FloatAccOp(code, *flags) {{
278 iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags)
279 header_output = BasicDeclare.subst(iop)
280 decoder_output = BasicConstructor.subst(iop)
281 decode_block = BasicDecode.subst(iop)
282 exec_output = BasicExecute.subst(iop)
283}};
284
285// Primary format for float64 operate instructions:
286def format Float64Op(code, *flags) {{
287 iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
288 header_output = BasicDeclare.subst(iop)
289 decoder_output = BasicConstructor.subst(iop)
290 decode_block = BasicDecode.subst(iop)
291 exec_output = BasicExecute.subst(iop)
292}};
293
294def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
295 import sys
296
297 code = 'bool cond1, cond2;\n'
298 code += 'bool code_block1, code_block2;\n'
299 code += 'code_block1 = code_block2 = true;\n'
300
301 if 'QnanException' in flags:
302 code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n'
303 code += '\tFCSR = genInvalidVector(FCSR);\n'
304 code += 'code_block1 = false;'
305 code += '}\n'
306 code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n'
307 code += '\tFCSR = genInvalidVector(FCSR);\n'
308 code += 'code_block2 = false;'
309 code += '}\n'
310
311 code += 'if (code_block1) {'
312 code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n'
313 if 'UnorderedTrue' in flags:
314 code += 'cond1 = 1;\n'
315 elif 'UnorderedFalse' in flags:
316 code += 'cond1 = 0;\n'
317 else:
318 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
319 code += '} else {\n'
320 code += cond_code1
321 code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n'
322
323 code += 'if (code_block2) {'
324 code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n'
325 if 'UnorderedTrue' in flags:
326 code += 'cond2 = 1;\n'
327 elif 'UnorderedFalse' in flags:
328 code += 'cond2 = 0;\n'
329 else:
330 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
331 code += '} else {\n'
332 code += cond_code2
333 code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}'
334
335 iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code))
336 header_output = BasicDeclare.subst(iop)
337 decoder_output = BasicConstructor.subst(iop)
338 decode_block = BasicDecode.subst(iop)
339 exec_output = BasicExecute.subst(iop)
340}};
341
|