1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30
31////////////////////////////////////////////////////////////////////
32//
33// Floating Point operate instructions
34//
35
36output header {{
37 /**
38 * Base class for FP operations.
39 */
40 class FPOp : public MipsStaticInst
41 {
42 protected:
43
44 /// Constructor
45 FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
46 {
47 }
48
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30
31////////////////////////////////////////////////////////////////////
32//
33// Floating Point operate instructions
34//
35
36output header {{
37 /**
38 * Base class for FP operations.
39 */
40 class FPOp : public MipsStaticInst
41 {
42 protected:
43
44 /// Constructor
45 FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
46 {
47 }
48
|
63 };
64}};
65
66output decoder {{
67 std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
68 {
69 std::stringstream ss;
70
71 ccprintf(ss, "%-10s ", mnemonic);
72
73 ccprintf(ss,"%d",CC);
74
75 if(_numSrcRegs > 0) {
76 ss << ", ";
77 printReg(ss, _srcRegIdx[0]);
78 }
79
80 if(_numSrcRegs > 1) {
81 ss << ", ";
82 printReg(ss, _srcRegIdx[1]);
83 }
84
85 return ss.str();
86 }
87}};
88
89output header {{
90 void fpResetCauseBits(ExecContext *cpu);
91
92}};
93
94output exec {{
95 inline Fault checkFpEnableFault(ExecContext *xc)
96 {
97 //@TODO: Implement correct CP0 checks to see if the CP1
98 // unit is enable or not
99 if (!isCoprocessorEnabled(xc, 1))
100 return std::make_shared<CoprocessorUnusableFault>(1);
101
102 return NoFault;
103 }
104
105 //If any operand is Nan return the appropriate QNaN
106 template <class T>
107 bool
108 fpNanOperands(FPOp *inst, ExecContext *xc, const T &src_type,
109 Trace::InstRecord *traceData)
110 {
111 uint64_t mips_nan = 0;
112 assert(sizeof(T) == 4);
113
114 for (int i = 0; i < inst->numSrcRegs(); i++) {
115 uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0);
116
117 if (isNan(&src_bits, 32) ) {
118 mips_nan = MIPS32_QNAN;
119 xc->setFloatRegOperandBits(inst, 0, mips_nan);
120 if (traceData) { traceData->setData(mips_nan); }
121 return true;
122 }
123 }
124 return false;
125 }
126
127 template <class T>
128 bool
129 fpInvalidOp(FPOp *inst, ExecContext *cpu, const T dest_val,
130 Trace::InstRecord *traceData)
131 {
132 uint64_t mips_nan = 0;
133 T src_op = dest_val;
134 assert(sizeof(T) == 4);
135
136 if (isNan(&src_op, 32)) {
137 mips_nan = MIPS32_QNAN;
138
139 //Set value to QNAN
140 cpu->setFloatRegOperandBits(inst, 0, mips_nan);
141
142 //Read FCSR from FloatRegFile
143 uint32_t fcsr_bits =
144 cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
145
146 uint32_t new_fcsr = genInvalidVector(fcsr_bits);
147
148 //Write FCSR from FloatRegFile
149 cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, new_fcsr);
150
151 if (traceData) { traceData->setData(mips_nan); }
152 return true;
153 }
154
155 return false;
156 }
157
158 void
159 fpResetCauseBits(ExecContext *cpu)
160 {
161 //Read FCSR from FloatRegFile
162 uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
163
164 // TODO: Use utility function here
165 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
166
167 //Write FCSR from FloatRegFile
168 cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr);
169 }
170}};
171
172def template FloatingPointExecute {{
173 Fault %(class_name)s::execute(
174 ExecContext *xc, Trace::InstRecord *traceData) const
175 {
176 Fault fault = NoFault;
177
178 %(fp_enable_check)s;
179
180
181 //When is the right time to reset cause bits?
182 //start of every instruction or every cycle?
183 if (FullSystem)
184 fpResetCauseBits(xc);
185 %(op_decl)s;
186 %(op_rd)s;
187
188 //Check if any FP operand is a NaN value
189 if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) {
190 %(code)s;
191
192 //Change this code for Full-System/Sycall Emulation
193 //separation
194 //----
195 //Should Full System-Mode throw a fault here?
196 //----
197 //Check for IEEE 754 FP Exceptions
198 //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
199 bool invalid_op = false;
200 if (FullSystem) {
201 invalid_op =
202 fpInvalidOp((FPOp*)this, xc, Fd, traceData);
203 }
204 if (!invalid_op && fault == NoFault) {
205 %(op_wb)s;
206 }
207 }
208
209 return fault;
210 }
211}};
212
213// Primary format for float point operate instructions:
214def format FloatOp(code, *flags) {{
215 iop = InstObjParams(name, Name, 'FPOp', code, flags)
216 header_output = BasicDeclare.subst(iop)
217 decoder_output = BasicConstructor.subst(iop)
218 decode_block = BasicDecode.subst(iop)
219 exec_output = FloatingPointExecute.subst(iop)
220}};
221
222def format FloatCompareOp(cond_code, *flags) {{
223 import sys
224
225 code = 'bool cond;\n'
226 if '_sf' in cond_code or 'SinglePrecision' in flags:
227 if 'QnanException' in flags:
228 code += 'if (isQnan(&Fs_sf, 32) || isQnan(&Ft_sf, 32)) {\n'
229 code += '\tFCSR = genInvalidVector(FCSR);\n'
230 code += '\treturn NoFault;'
231 code += '}\n else '
232 code += 'if (isNan(&Fs_sf, 32) || isNan(&Ft_sf, 32)) {\n'
233 elif '_df' in cond_code or 'DoublePrecision' in flags:
234 if 'QnanException' in flags:
235 code += 'if (isQnan(&Fs_df, 64) || isQnan(&Ft_df, 64)) {\n'
236 code += '\tFCSR = genInvalidVector(FCSR);\n'
237 code += '\treturn NoFault;'
238 code += '}\n else '
239 code += 'if (isNan(&Fs_df, 64) || isNan(&Ft_df, 64)) {\n'
240 else:
241 sys.exit('Decoder Failed: Can\'t Determine Operand Type\n')
242
243 if 'UnorderedTrue' in flags:
244 code += 'cond = 1;\n'
245 elif 'UnorderedFalse' in flags:
246 code += 'cond = 0;\n'
247 else:
248 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
249
250 code += '} else {\n'
251 code += cond_code + '}'
252 code += 'FCSR = genCCVector(FCSR, CC, cond);\n'
253
254 iop = InstObjParams(name, Name, 'FPCompareOp', code)
255 header_output = BasicDeclare.subst(iop)
256 decoder_output = BasicConstructor.subst(iop)
257 decode_block = BasicDecode.subst(iop)
258 exec_output = BasicExecute.subst(iop)
259}};
260
261def format FloatConvertOp(code, *flags) {{
262 import sys
263
264 #Determine Source Type
265 convert = 'fpConvert('
266 if '_sf' in code:
267 code = 'float ' + code + '\n'
268 convert += 'SINGLE_TO_'
269 elif '_df' in code:
270 code = 'double ' + code + '\n'
271 convert += 'DOUBLE_TO_'
272 elif '_sw' in code:
273 code = 'int32_t ' + code + '\n'
274 convert += 'WORD_TO_'
275 elif '_sd' in code:
276 code = 'int64_t ' + code + '\n'
277 convert += 'LONG_TO_'
278 else:
279 sys.exit("Error Determining Source Type for Conversion")
280
281 #Determine Destination Type
282 if 'ToSingle' in flags:
283 code += 'Fd_uw = ' + convert + 'SINGLE, '
284 elif 'ToDouble' in flags:
285 code += 'Fd_ud = ' + convert + 'DOUBLE, '
286 elif 'ToWord' in flags:
287 code += 'Fd_uw = ' + convert + 'WORD, '
288 elif 'ToLong' in flags:
289 code += 'Fd_ud = ' + convert + 'LONG, '
290 else:
291 sys.exit("Error Determining Destination Type for Conversion")
292
293 #Figure out how to round value
294 if 'Ceil' in flags:
295 code += 'ceil(val)); '
296 elif 'Floor' in flags:
297 code += 'floor(val)); '
298 elif 'Round' in flags:
299 code += 'roundFP(val, 0)); '
300 elif 'Trunc' in flags:
301 code += 'truncFP(val));'
302 else:
303 code += 'val); '
304
305 iop = InstObjParams(name, Name, 'FPOp', code)
306 header_output = BasicDeclare.subst(iop)
307 decoder_output = BasicConstructor.subst(iop)
308 decode_block = BasicDecode.subst(iop)
309 exec_output = BasicExecute.subst(iop)
310}};
311
312def format FloatAccOp(code, *flags) {{
313 iop = InstObjParams(name, Name, 'FPOp', code, flags)
314 header_output = BasicDeclare.subst(iop)
315 decoder_output = BasicConstructor.subst(iop)
316 decode_block = BasicDecode.subst(iop)
317 exec_output = BasicExecute.subst(iop)
318}};
319
320// Primary format for float64 operate instructions:
321def format Float64Op(code, *flags) {{
322 iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
323 header_output = BasicDeclare.subst(iop)
324 decoder_output = BasicConstructor.subst(iop)
325 decode_block = BasicDecode.subst(iop)
326 exec_output = BasicExecute.subst(iop)
327}};
328
329def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
330 import sys
331
332 code = 'bool cond1, cond2;\n'
333 code += 'bool code_block1, code_block2;\n'
334 code += 'code_block1 = code_block2 = true;\n'
335
336 if 'QnanException' in flags:
337 code += 'if (isQnan(&Fs1_sf, 32) || isQnan(&Ft1_sf, 32)) {\n'
338 code += '\tFCSR = genInvalidVector(FCSR);\n'
339 code += 'code_block1 = false;'
340 code += '}\n'
341 code += 'if (isQnan(&Fs2_sf, 32) || isQnan(&Ft2_sf, 32)) {\n'
342 code += '\tFCSR = genInvalidVector(FCSR);\n'
343 code += 'code_block2 = false;'
344 code += '}\n'
345
346 code += 'if (code_block1) {'
347 code += '\tif (isNan(&Fs1_sf, 32) || isNan(&Ft1_sf, 32)) {\n'
348 if 'UnorderedTrue' in flags:
349 code += 'cond1 = 1;\n'
350 elif 'UnorderedFalse' in flags:
351 code += 'cond1 = 0;\n'
352 else:
353 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
354 code += '} else {\n'
355 code += cond_code1
356 code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n'
357
358 code += 'if (code_block2) {'
359 code += '\tif (isNan(&Fs2_sf, 32) || isNan(&Ft2_sf, 32)) {\n'
360 if 'UnorderedTrue' in flags:
361 code += 'cond2 = 1;\n'
362 elif 'UnorderedFalse' in flags:
363 code += 'cond2 = 0;\n'
364 else:
365 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
366 code += '} else {\n'
367 code += cond_code2
368 code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}'
369
370 iop = InstObjParams(name, Name, 'FPCompareOp', code)
371 header_output = BasicDeclare.subst(iop)
372 decoder_output = BasicConstructor.subst(iop)
373 decode_block = BasicDecode.subst(iop)
374 exec_output = BasicExecute.subst(iop)
375}};
376
| 61 };
62}};
63
64output decoder {{
65 std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
66 {
67 std::stringstream ss;
68
69 ccprintf(ss, "%-10s ", mnemonic);
70
71 ccprintf(ss,"%d",CC);
72
73 if(_numSrcRegs > 0) {
74 ss << ", ";
75 printReg(ss, _srcRegIdx[0]);
76 }
77
78 if(_numSrcRegs > 1) {
79 ss << ", ";
80 printReg(ss, _srcRegIdx[1]);
81 }
82
83 return ss.str();
84 }
85}};
86
87output header {{
88 void fpResetCauseBits(ExecContext *cpu);
89
90}};
91
92output exec {{
93 inline Fault checkFpEnableFault(ExecContext *xc)
94 {
95 //@TODO: Implement correct CP0 checks to see if the CP1
96 // unit is enable or not
97 if (!isCoprocessorEnabled(xc, 1))
98 return std::make_shared<CoprocessorUnusableFault>(1);
99
100 return NoFault;
101 }
102
103 //If any operand is Nan return the appropriate QNaN
104 template <class T>
105 bool
106 fpNanOperands(FPOp *inst, ExecContext *xc, const T &src_type,
107 Trace::InstRecord *traceData)
108 {
109 uint64_t mips_nan = 0;
110 assert(sizeof(T) == 4);
111
112 for (int i = 0; i < inst->numSrcRegs(); i++) {
113 uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0);
114
115 if (isNan(&src_bits, 32) ) {
116 mips_nan = MIPS32_QNAN;
117 xc->setFloatRegOperandBits(inst, 0, mips_nan);
118 if (traceData) { traceData->setData(mips_nan); }
119 return true;
120 }
121 }
122 return false;
123 }
124
125 template <class T>
126 bool
127 fpInvalidOp(FPOp *inst, ExecContext *cpu, const T dest_val,
128 Trace::InstRecord *traceData)
129 {
130 uint64_t mips_nan = 0;
131 T src_op = dest_val;
132 assert(sizeof(T) == 4);
133
134 if (isNan(&src_op, 32)) {
135 mips_nan = MIPS32_QNAN;
136
137 //Set value to QNAN
138 cpu->setFloatRegOperandBits(inst, 0, mips_nan);
139
140 //Read FCSR from FloatRegFile
141 uint32_t fcsr_bits =
142 cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
143
144 uint32_t new_fcsr = genInvalidVector(fcsr_bits);
145
146 //Write FCSR from FloatRegFile
147 cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, new_fcsr);
148
149 if (traceData) { traceData->setData(mips_nan); }
150 return true;
151 }
152
153 return false;
154 }
155
156 void
157 fpResetCauseBits(ExecContext *cpu)
158 {
159 //Read FCSR from FloatRegFile
160 uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
161
162 // TODO: Use utility function here
163 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
164
165 //Write FCSR from FloatRegFile
166 cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr);
167 }
168}};
169
170def template FloatingPointExecute {{
171 Fault %(class_name)s::execute(
172 ExecContext *xc, Trace::InstRecord *traceData) const
173 {
174 Fault fault = NoFault;
175
176 %(fp_enable_check)s;
177
178
179 //When is the right time to reset cause bits?
180 //start of every instruction or every cycle?
181 if (FullSystem)
182 fpResetCauseBits(xc);
183 %(op_decl)s;
184 %(op_rd)s;
185
186 //Check if any FP operand is a NaN value
187 if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) {
188 %(code)s;
189
190 //Change this code for Full-System/Sycall Emulation
191 //separation
192 //----
193 //Should Full System-Mode throw a fault here?
194 //----
195 //Check for IEEE 754 FP Exceptions
196 //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
197 bool invalid_op = false;
198 if (FullSystem) {
199 invalid_op =
200 fpInvalidOp((FPOp*)this, xc, Fd, traceData);
201 }
202 if (!invalid_op && fault == NoFault) {
203 %(op_wb)s;
204 }
205 }
206
207 return fault;
208 }
209}};
210
211// Primary format for float point operate instructions:
212def format FloatOp(code, *flags) {{
213 iop = InstObjParams(name, Name, 'FPOp', code, flags)
214 header_output = BasicDeclare.subst(iop)
215 decoder_output = BasicConstructor.subst(iop)
216 decode_block = BasicDecode.subst(iop)
217 exec_output = FloatingPointExecute.subst(iop)
218}};
219
220def format FloatCompareOp(cond_code, *flags) {{
221 import sys
222
223 code = 'bool cond;\n'
224 if '_sf' in cond_code or 'SinglePrecision' in flags:
225 if 'QnanException' in flags:
226 code += 'if (isQnan(&Fs_sf, 32) || isQnan(&Ft_sf, 32)) {\n'
227 code += '\tFCSR = genInvalidVector(FCSR);\n'
228 code += '\treturn NoFault;'
229 code += '}\n else '
230 code += 'if (isNan(&Fs_sf, 32) || isNan(&Ft_sf, 32)) {\n'
231 elif '_df' in cond_code or 'DoublePrecision' in flags:
232 if 'QnanException' in flags:
233 code += 'if (isQnan(&Fs_df, 64) || isQnan(&Ft_df, 64)) {\n'
234 code += '\tFCSR = genInvalidVector(FCSR);\n'
235 code += '\treturn NoFault;'
236 code += '}\n else '
237 code += 'if (isNan(&Fs_df, 64) || isNan(&Ft_df, 64)) {\n'
238 else:
239 sys.exit('Decoder Failed: Can\'t Determine Operand Type\n')
240
241 if 'UnorderedTrue' in flags:
242 code += 'cond = 1;\n'
243 elif 'UnorderedFalse' in flags:
244 code += 'cond = 0;\n'
245 else:
246 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
247
248 code += '} else {\n'
249 code += cond_code + '}'
250 code += 'FCSR = genCCVector(FCSR, CC, cond);\n'
251
252 iop = InstObjParams(name, Name, 'FPCompareOp', code)
253 header_output = BasicDeclare.subst(iop)
254 decoder_output = BasicConstructor.subst(iop)
255 decode_block = BasicDecode.subst(iop)
256 exec_output = BasicExecute.subst(iop)
257}};
258
259def format FloatConvertOp(code, *flags) {{
260 import sys
261
262 #Determine Source Type
263 convert = 'fpConvert('
264 if '_sf' in code:
265 code = 'float ' + code + '\n'
266 convert += 'SINGLE_TO_'
267 elif '_df' in code:
268 code = 'double ' + code + '\n'
269 convert += 'DOUBLE_TO_'
270 elif '_sw' in code:
271 code = 'int32_t ' + code + '\n'
272 convert += 'WORD_TO_'
273 elif '_sd' in code:
274 code = 'int64_t ' + code + '\n'
275 convert += 'LONG_TO_'
276 else:
277 sys.exit("Error Determining Source Type for Conversion")
278
279 #Determine Destination Type
280 if 'ToSingle' in flags:
281 code += 'Fd_uw = ' + convert + 'SINGLE, '
282 elif 'ToDouble' in flags:
283 code += 'Fd_ud = ' + convert + 'DOUBLE, '
284 elif 'ToWord' in flags:
285 code += 'Fd_uw = ' + convert + 'WORD, '
286 elif 'ToLong' in flags:
287 code += 'Fd_ud = ' + convert + 'LONG, '
288 else:
289 sys.exit("Error Determining Destination Type for Conversion")
290
291 #Figure out how to round value
292 if 'Ceil' in flags:
293 code += 'ceil(val)); '
294 elif 'Floor' in flags:
295 code += 'floor(val)); '
296 elif 'Round' in flags:
297 code += 'roundFP(val, 0)); '
298 elif 'Trunc' in flags:
299 code += 'truncFP(val));'
300 else:
301 code += 'val); '
302
303 iop = InstObjParams(name, Name, 'FPOp', code)
304 header_output = BasicDeclare.subst(iop)
305 decoder_output = BasicConstructor.subst(iop)
306 decode_block = BasicDecode.subst(iop)
307 exec_output = BasicExecute.subst(iop)
308}};
309
310def format FloatAccOp(code, *flags) {{
311 iop = InstObjParams(name, Name, 'FPOp', code, flags)
312 header_output = BasicDeclare.subst(iop)
313 decoder_output = BasicConstructor.subst(iop)
314 decode_block = BasicDecode.subst(iop)
315 exec_output = BasicExecute.subst(iop)
316}};
317
318// Primary format for float64 operate instructions:
319def format Float64Op(code, *flags) {{
320 iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
321 header_output = BasicDeclare.subst(iop)
322 decoder_output = BasicConstructor.subst(iop)
323 decode_block = BasicDecode.subst(iop)
324 exec_output = BasicExecute.subst(iop)
325}};
326
327def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
328 import sys
329
330 code = 'bool cond1, cond2;\n'
331 code += 'bool code_block1, code_block2;\n'
332 code += 'code_block1 = code_block2 = true;\n'
333
334 if 'QnanException' in flags:
335 code += 'if (isQnan(&Fs1_sf, 32) || isQnan(&Ft1_sf, 32)) {\n'
336 code += '\tFCSR = genInvalidVector(FCSR);\n'
337 code += 'code_block1 = false;'
338 code += '}\n'
339 code += 'if (isQnan(&Fs2_sf, 32) || isQnan(&Ft2_sf, 32)) {\n'
340 code += '\tFCSR = genInvalidVector(FCSR);\n'
341 code += 'code_block2 = false;'
342 code += '}\n'
343
344 code += 'if (code_block1) {'
345 code += '\tif (isNan(&Fs1_sf, 32) || isNan(&Ft1_sf, 32)) {\n'
346 if 'UnorderedTrue' in flags:
347 code += 'cond1 = 1;\n'
348 elif 'UnorderedFalse' in flags:
349 code += 'cond1 = 0;\n'
350 else:
351 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
352 code += '} else {\n'
353 code += cond_code1
354 code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n'
355
356 code += 'if (code_block2) {'
357 code += '\tif (isNan(&Fs2_sf, 32) || isNan(&Ft2_sf, 32)) {\n'
358 if 'UnorderedTrue' in flags:
359 code += 'cond2 = 1;\n'
360 elif 'UnorderedFalse' in flags:
361 code += 'cond2 = 0;\n'
362 else:
363 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
364 code += '} else {\n'
365 code += cond_code2
366 code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}'
367
368 iop = InstObjParams(name, Name, 'FPCompareOp', code)
369 header_output = BasicDeclare.subst(iop)
370 decoder_output = BasicConstructor.subst(iop)
371 decode_block = BasicDecode.subst(iop)
372 exec_output = BasicExecute.subst(iop)
373}};
374
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