1// -*- mode:c++ -*-
2
3// Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
4
5// This software is part of the M5 simulator.
6
7// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
8// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
9// TO THESE TERMS AND CONDITIONS.
10
11// Permission is granted to use, copy, create derivative works and
12// distribute this software and such derivative works for any purpose,
13// so long as (1) the copyright notice above, this grant of permission,
14// and the disclaimer below appear in all copies and derivative works
15// made, (2) the copyright notice above is augmented as appropriate to
16// reflect the addition of any new copyrightable work in a derivative
17// work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
18// the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
19// advertising or publicity pertaining to the use or distribution of
20// this software without specific, written prior authorization.
21
22// THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND
23// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
24// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
26// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
27// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
28// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
29// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
30// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
31// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
32// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
33// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
34
35//Authors: Korey L. Sewell
36
37////////////////////////////////////////////////////////////////////
38//
39// Floating Point operate instructions
40//
41
42output header {{
43 /**
44 * Base class for FP operations.

--- 47 unchanged lines hidden (view full) ---

92 }
93}};
94
95output exec {{
96 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
97 {
98 //@TODO: Implement correct CP0 checks to see if the CP1
99 // unit is enable or not
100 if (!isCoprocessorEnabled(xc, 1))
101 return new CoprocessorUnusableFault(1);
102
103 return NoFault;
104 }
105
106 //If any operand is Nan return the appropriate QNaN
107 template <class T>
108 bool
109 fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type,
110 Trace::InstRecord *traceData)
111 {

--- 75 unchanged lines hidden (view full) ---

187
188def template FloatingPointExecute {{
189 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
190 {
191 Fault fault = NoFault;
192
193 %(fp_enable_check)s;
194
195
196 //When is the right time to reset cause bits?
197 //start of every instruction or every cycle?
198#if FULL_SYSTEM
199 fpResetCauseBits(xc);
200#endif
201 %(op_decl)s;
202 %(op_rd)s;
203

--- 189 unchanged lines hidden ---