dsp.isa (9554:406fbcf60223) dsp.isa (10196:be0e1724eb39)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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59 MipsStaticInst(mnem, _machInst, __opClass)
60 {
61 }
62 };
63}};
64
65// Dsp instruction class execute method template.
66def template DspExecute {{
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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59 MipsStaticInst(mnem, _machInst, __opClass)
60 {
61 }
62 };
63}};
64
65// Dsp instruction class execute method template.
66def template DspExecute {{
67 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
67 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
68 {
69 Fault fault = NoFault;
70
71 %(op_decl)s;
72
73 if (isDspPresent(xc))
74 {
75 if (isDspEnabled(xc))

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92 %(op_wb)s;
93 }
94 return fault;
95 }
96}};
97
98// DspHiLo instruction class execute method template.
99def template DspHiLoExecute {{
68 {
69 Fault fault = NoFault;
70
71 %(op_decl)s;
72
73 if (isDspPresent(xc))
74 {
75 if (isDspEnabled(xc))

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92 %(op_wb)s;
93 }
94 return fault;
95 }
96}};
97
98// DspHiLo instruction class execute method template.
99def template DspHiLoExecute {{
100 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
100 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
101 {
102 Fault fault = NoFault;
103
104 %(op_decl)s;
105
106 if (isDspPresent(xc))
107 {
108 if (isDspEnabled(xc))

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142}};
143
144//Outputs to decoder.cc
145output decoder {{
146}};
147
148output exec {{
149 bool
101 {
102 Fault fault = NoFault;
103
104 %(op_decl)s;
105
106 if (isDspPresent(xc))
107 {
108 if (isDspEnabled(xc))

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142}};
143
144//Outputs to decoder.cc
145output decoder {{
146}};
147
148output exec {{
149 bool
150 isDspEnabled(%(CPU_exec_context)s *xc)
150 isDspEnabled(CPU_EXEC_CONTEXT *xc)
151 {
152 return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24);
153 }
154}};
155
156output exec {{
157 bool
151 {
152 return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24);
153 }
154}};
155
156output exec {{
157 bool
158 isDspPresent(%(CPU_exec_context)s *xc)
158 isDspPresent(CPU_EXEC_CONTEXT *xc)
159 {
160 return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
161 }
162}};
163
164// add code to fetch the DSPControl register
165// and write it back after execution, giving
166// the instruction the opportunity to modify

--- 53 unchanged lines hidden --- 		159 {
160 return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
161 }
162}};
163
164// add code to fetch the DSPControl register
165// and write it back after execution, giving
166// the instruction the opportunity to modify

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