dsp.isa (8564:f81bcb16fa1b) dsp.isa (8738:66bf413b0d5b)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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138//Outputs to decoder.cc
139output decoder {{
140}};
141
142output exec {{
143 bool
144 isDspEnabled(%(CPU_exec_context)s *xc)
145 {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 129 unchanged lines hidden (view full) ---

138//Outputs to decoder.cc
139output decoder {{
140}};
141
142output exec {{
143 bool
144 isDspEnabled(%(CPU_exec_context)s *xc)
145 {
146 return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_STATUS), 24);
146 return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24);
147 }
148}};
149
150output exec {{
151 bool
152 isDspPresent(%(CPU_exec_context)s *xc)
153 {
147 }
148}};
149
150output exec {{
151 bool
152 isDspPresent(%(CPU_exec_context)s *xc)
153 {
154 return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
154 return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
155 }
156}};
157
158// add code to fetch the DSPControl register
159// and write it back after execution, giving
160// the instruction the opportunity to modify
161// it if necessary
162def format DspIntOp(code, *opt_flags) {{

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156}};
157
158// add code to fetch the DSPControl register
159// and write it back after execution, giving
160// the instruction the opportunity to modify
161// it if necessary
162def format DspIntOp(code, *opt_flags) {{

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