dsp.isa (10474:799c8ee4ecba) dsp.isa (12234:78ece221f9f5)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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59 MipsStaticInst(mnem, _machInst, __opClass)
60 {
61 }
62 };
63}};
64
65// Dsp instruction class execute method template.
66def template DspExecute {{
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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59 MipsStaticInst(mnem, _machInst, __opClass)
60 {
61 }
62 };
63}};
64
65// Dsp instruction class execute method template.
66def template DspExecute {{
67 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
67 Fault %(class_name)s::execute(
68 ExecContext *xc, Trace::InstRecord *traceData) const
68 {
69 Fault fault = NoFault;
70
71 %(op_decl)s;
72
73 if (isDspPresent(xc))
74 {
75 if (isDspEnabled(xc))

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92 %(op_wb)s;
93 }
94 return fault;
95 }
96}};
97
98// DspHiLo instruction class execute method template.
99def template DspHiLoExecute {{
69 {
70 Fault fault = NoFault;
71
72 %(op_decl)s;
73
74 if (isDspPresent(xc))
75 {
76 if (isDspEnabled(xc))

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93 %(op_wb)s;
94 }
95 return fault;
96 }
97}};
98
99// DspHiLo instruction class execute method template.
100def template DspHiLoExecute {{
100 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
101 Fault %(class_name)s::execute(
102 ExecContext *xc, Trace::InstRecord *traceData) const
101 {
102 Fault fault = NoFault;
103
104 %(op_decl)s;
105
106 if (isDspPresent(xc))
107 {
108 if (isDspEnabled(xc))

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131 //traceData->setData(hilo_final_val);
132 }
133 }
134 return fault;
135 }
136}};
137
138output header {{
103 {
104 Fault fault = NoFault;
105
106 %(op_decl)s;
107
108 if (isDspPresent(xc))
109 {
110 if (isDspEnabled(xc))

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133 //traceData->setData(hilo_final_val);
134 }
135 }
136 return fault;
137 }
138}};
139
140output header {{
139 bool isDspEnabled(%(CPU_exec_context)s *xc);
141 bool isDspEnabled(ExecContext *xc);
140
142
141 bool isDspPresent(%(CPU_exec_context)s *xc);
143 bool isDspPresent(ExecContext *xc);
142}};
143
144//Outputs to decoder.cc
145output decoder {{
146}};
147
148output exec {{
149 bool
144}};
145
146//Outputs to decoder.cc
147output decoder {{
148}};
149
150output exec {{
151 bool
150 isDspEnabled(CPU_EXEC_CONTEXT *xc)
152 isDspEnabled(ExecContext *xc)
151 {
152 return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24);
153 }
154}};
155
156output exec {{
157 bool
153 {
154 return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24);
155 }
156}};
157
158output exec {{
159 bool
158 isDspPresent(CPU_EXEC_CONTEXT *xc)
160 isDspPresent(ExecContext *xc)
159 {
160 return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
161 }
162}};
163
164// add code to fetch the DSPControl register
165// and write it back after execution, giving
166// the instruction the opportunity to modify

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162 return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
163 }
164}};
165
166// add code to fetch the DSPControl register
167// and write it back after execution, giving
168// the instruction the opportunity to modify

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