control.isa (6383:31c067ae3331) control.isa (8564:f81bcb16fa1b)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 110 unchanged lines hidden (view full) ---

119 }
120 return fault;
121 }
122}};
123// Basic instruction class execute method template.
124def template ControlTLBExecute {{
125 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
126 {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 110 unchanged lines hidden (view full) ---

119 }
120 return fault;
121 }
122}};
123// Basic instruction class execute method template.
124def template ControlTLBExecute {{
125 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
126 {
127 Fault fault = NoFault;
128 %(op_decl)s;
129 %(op_rd)s;
127 Fault fault = NoFault;
128 %(op_decl)s;
129 %(op_rd)s;
130
130
131#if FULL_SYSTEM
131 if (FULL_SYSTEM) {
132 if (isCoprocessor0Enabled(xc)) {
132 if (isCoprocessor0Enabled(xc)) {
133 if(isMMUTLB(xc)){
134 %(code)s;
135 } else {
136 fault = new ReservedInstructionFault();
137 }
133 if(isMMUTLB(xc)){
134 %(code)s;
135 } else {
136 fault = new ReservedInstructionFault();
137 }
138 } else {
138 } else {
139 fault = new CoprocessorUnusableFault(0);
139 fault = new CoprocessorUnusableFault(0);
140 }
140 }
141#else // Syscall Emulation Mode - No TLB Instructions
141 } else { // Syscall Emulation Mode - No TLB Instructions
142 fault = new ReservedInstructionFault();
142 fault = new ReservedInstructionFault();
143#endif
143 }
144
144
145 if(fault == NoFault)
146 {
147 %(op_wb)s;
148 }
149 return fault;
150
145 if (fault == NoFault) {
146 %(op_wb)s;
147 }
148 return fault;
151 }
152}};
153
154//Outputs to decoder.cc
155output decoder {{
156 std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
157 {
158 std::stringstream ss;

--- 11 unchanged lines hidden (view full) ---

170 std::stringstream ss;
171 ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
172 return ss.str();
173 }
174
175}};
176
177output exec {{
149 }
150}};
151
152//Outputs to decoder.cc
153output decoder {{
154 std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
155 {
156 std::stringstream ss;

--- 11 unchanged lines hidden (view full) ---

168 std::stringstream ss;
169 ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
170 return ss.str();
171 }
172
173}};
174
175output exec {{
178 bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
176 bool
177 isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
179 {
178 {
180#if !FULL_SYSTEM
181 return true;
182#else
183 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
184 switch(cop_num)
185 {
186 case 0:
187 {
188 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
189 if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
190 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
191 && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
192 // Unable to use Status_CU0, etc directly, using bitfields & masks
193 return false;
194 }
179 if (!FULL_SYSTEM)
180 return true;
195
181
196 }
197 break;
198 case 1:
199 if((Stat & 0x20000000) == 0) // CU1 is reset
200 return false;
201 break;
202 case 2:
203 if((Stat & 0x40000000) == 0) // CU2 is reset
204 return false;
205 break;
206 case 3:
207 if((Stat & 0x80000000) == 0) // CU3 is reset
208 return false;
209 break;
210 default: panic("Invalid Coprocessor Number Specified");
211 break;
182 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
183 if (cop_num == 0) {
184 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
185 // In Stat, EXL, ERL or CU0 set, CP0 accessible
186 // In Dbg, DM bit set, CP0 accessible
187 // In Stat, KSU = 0, kernel mode is base mode
188 return (Stat & 0x10000006) ||
189 (Dbg & 0x40000000) ||
190 !(Stat & 0x00000018);
191 } else if (cop_num < 4) {
192 return Stat & (0x10000000 << cop_num); // CU is reset
193 } else {
194 panic("Invalid Coprocessor Number Specified");
212 }
195 }
213 return true;
214#endif
215 }
196 }
216 bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
197
198 bool inline
199 isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
217 {
200 {
218#if FULL_SYSTEM
219 MiscReg Stat = xc->readMiscRegNoEffect(MISCREG_STATUS);
220 MiscReg Dbg = xc->readMiscRegNoEffect(MISCREG_DEBUG);
221 if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
222 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
223 && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
224 // Unable to use Status_CU0, etc directly, using bitfields & masks
225 return false;
226 }
227#else
228 //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
229#endif
230 return true;
201 if (FULL_SYSTEM) {
202 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
203 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
204 // In Stat, EXL, ERL or CU0 set, CP0 accessible
205 // In Dbg, DM bit set, CP0 accessible
206 // In Stat KSU = 0, kernel mode is base mode
207 return (Stat & 0x10000006) || (Dbg & 0x40000000) ||
208 !(Stat & 0x00000018);
209 } else {
210 return true;
211 }
231 }
212 }
232 bool isMMUTLB(%(CPU_exec_context)s *xc)
213
214 bool
215 isMMUTLB(%(CPU_exec_context)s *xc)
233 {
216 {
234#if FULL_SYSTEM
235 if((xc->readMiscRegNoEffect(MISCREG_CONFIG) & 0x00000380)==0x80)
236 return true;
237#endif
238 return false;
217 MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
218 return FULL_SYSTEM && (Config & 0x380) == 0x80;
239 }
240}};
241
242def format CP0Control(code, *flags) {{
243 flags += ('IsNonSpeculative', )
244 iop = InstObjParams(name, Name, 'CP0Control', code, flags)
245 header_output = BasicDeclare.subst(iop)
246 decoder_output = BasicConstructor.subst(iop)

--- 21 unchanged lines hidden --- 		219 }
220}};
221
222def format CP0Control(code, *flags) {{
223 flags += ('IsNonSpeculative', )
224 iop = InstObjParams(name, Name, 'CP0Control', code, flags)
225 header_output = BasicDeclare.subst(iop)
226 decoder_output = BasicConstructor.subst(iop)

--- 21 unchanged lines hidden ---