control.isa (5268:5bfc53fe60e7) control.isa (6383:31c067ae3331)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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175}};
176
177output exec {{
178 bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
179 {
180#if !FULL_SYSTEM
181 return true;
182#else
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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175}};
176
177output exec {{
178 bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
179 {
180#if !FULL_SYSTEM
181 return true;
182#else
183 MiscReg Stat = xc->readMiscReg(MipsISA::Status);
183 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
184 switch(cop_num)
185 {
186 case 0:
187 {
184 switch(cop_num)
185 {
186 case 0:
187 {
188 MiscReg Dbg = xc->readMiscReg(MipsISA::Debug);
188 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
189 if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
190 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
191 && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
192 // Unable to use Status_CU0, etc directly, using bitfields & masks
193 return false;
194 }
195
196 }

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211 break;
212 }
213 return true;
214#endif
215 }
216 bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
217 {
218#if FULL_SYSTEM
189 if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
190 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
191 && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
192 // Unable to use Status_CU0, etc directly, using bitfields & masks
193 return false;
194 }
195
196 }

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211 break;
212 }
213 return true;
214#endif
215 }
216 bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
217 {
218#if FULL_SYSTEM
219 MiscReg Stat = xc->readMiscRegNoEffect(MipsISA::Status);
220 MiscReg Dbg = xc->readMiscRegNoEffect(MipsISA::Debug);
219 MiscReg Stat = xc->readMiscRegNoEffect(MISCREG_STATUS);
220 MiscReg Dbg = xc->readMiscRegNoEffect(MISCREG_DEBUG);
221 if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
222 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
223 && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
224 // Unable to use Status_CU0, etc directly, using bitfields & masks
225 return false;
226 }
227#else
228 //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
229#endif
230 return true;
231 }
232 bool isMMUTLB(%(CPU_exec_context)s *xc)
233 {
234#if FULL_SYSTEM
221 if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
222 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
223 && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
224 // Unable to use Status_CU0, etc directly, using bitfields & masks
225 return false;
226 }
227#else
228 //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
229#endif
230 return true;
231 }
232 bool isMMUTLB(%(CPU_exec_context)s *xc)
233 {
234#if FULL_SYSTEM
235 if((xc->readMiscRegNoEffect(MipsISA::Config) & 0x00000380)==0x80)
235 if((xc->readMiscRegNoEffect(MISCREG_CONFIG) & 0x00000380)==0x80)
236 return true;
237#endif
238 return false;
239 }
240}};
241
242def format CP0Control(code, *flags) {{
243 flags += ('IsNonSpeculative', )

--- 24 unchanged lines hidden --- 		236 return true;
237#endif
238 return false;
239 }
240}};
241
242def format CP0Control(code, *flags) {{
243 flags += ('IsNonSpeculative', )

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