control.isa (5222:bb733a878f85) control.isa (5224:0e354459fb8a)
1// -*- mode:c++ -*-
2
3// Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
4
5// This software is part of the M5 simulator.
6
7// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
8// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING

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178 return ss.str();
179 }
180
181}};
182
183output exec {{
184 bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
185 {
1// -*- mode:c++ -*-
2
3// Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
4
5// This software is part of the M5 simulator.
6
7// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
8// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING

--- 169 unchanged lines hidden (view full) ---

178 return ss.str();
179 }
180
181}};
182
183output exec {{
184 bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
185 {
186#if !FULL_SYSTEM
187 return true;
188#else
186 MiscReg Stat = xc->readMiscReg(MipsISA::Status);
187 switch(cop_num)
188 {
189 case 0:
190 {
189 MiscReg Stat = xc->readMiscReg(MipsISA::Status);
190 switch(cop_num)
191 {
192 case 0:
193 {
191#if FULL_SYSTEM
192 MiscReg Dbg = xc->readMiscReg(MipsISA::Debug);
193 if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
194 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
195 && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
196 // Unable to use Status_CU0, etc directly, using bitfields & masks
197 return false;
194 MiscReg Dbg = xc->readMiscReg(MipsISA::Debug);
195 if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
196 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
197 && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
198 // Unable to use Status_CU0, etc directly, using bitfields & masks
199 return false;
200 }
201
198 }
202 }
199#else
200 //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
201#endif
202 }
203 break;
204 case 1:
205 if((Stat & 0x20000000) == 0) // CU1 is reset
206 return false;
207 break;
208 case 2:
209 if((Stat & 0x40000000) == 0) // CU2 is reset
210 return false;
211 break;
212 case 3:
213 if((Stat & 0x80000000) == 0) // CU3 is reset
214 return false;
215 break;
216 default: panic("Invalid Coprocessor Number Specified");
217 break;
218 }
219 return true;
203 break;
204 case 1:
205 if((Stat & 0x20000000) == 0) // CU1 is reset
206 return false;
207 break;
208 case 2:
209 if((Stat & 0x40000000) == 0) // CU2 is reset
210 return false;
211 break;
212 case 3:
213 if((Stat & 0x80000000) == 0) // CU3 is reset
214 return false;
215 break;
216 default: panic("Invalid Coprocessor Number Specified");
217 break;
218 }
219 return true;
220#endif
220 }
221 bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
222 {
223#if FULL_SYSTEM
224 MiscReg Stat = xc->readMiscRegNoEffect(MipsISA::Status);
225 MiscReg Dbg = xc->readMiscRegNoEffect(MipsISA::Debug);
226 if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
227 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible

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222 bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
223 {
224#if FULL_SYSTEM
225 MiscReg Stat = xc->readMiscRegNoEffect(MipsISA::Status);
226 MiscReg Dbg = xc->readMiscRegNoEffect(MipsISA::Debug);
227 if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
228 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible

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