control.isa (4661:44458219add1) | control.isa (5222:bb733a878f85) |
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1// -*- mode:c++ -*- 2 | 1// -*- mode:c++ -*- 2 |
3// Copyright (c) 2006 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell | 3// Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved |
30 | 4 |
5// This software is part of the M5 simulator. 6 7// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 8// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 9// TO THESE TERMS AND CONDITIONS. 10 11// Permission is granted to use, copy, create derivative works and 12// distribute this software and such derivative works for any purpose, 13// so long as (1) the copyright notice above, this grant of permission, 14// and the disclaimer below appear in all copies and derivative works 15// made, (2) the copyright notice above is augmented as appropriate to 16// reflect the addition of any new copyrightable work in a derivative 17// work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3) 18// the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any 19// advertising or publicity pertaining to the use or distribution of 20// this software without specific, written prior authorization. 21 22// THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND 23// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 24// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 26// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 27// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 28// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 29// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 30// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 31// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 32// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 33// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 34 35//Authors: Korey L. Sewell 36// Jaidev Patwardhan 37 |
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31//////////////////////////////////////////////////////////////////// 32// 33// Coprocessor instructions 34// 35 36//Outputs to decoder.hh 37output header {{ 38 --- 4 unchanged lines hidden (view full) --- 43 /// Constructor 44 CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) : 45 MipsStaticInst(mnem, _machInst, __opClass) 46 { 47 } 48 49 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 50 }; | 38//////////////////////////////////////////////////////////////////// 39// 40// Coprocessor instructions 41// 42 43//Outputs to decoder.hh 44output header {{ 45 --- 4 unchanged lines hidden (view full) --- 50 /// Constructor 51 CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) : 52 MipsStaticInst(mnem, _machInst, __opClass) 53 { 54 } 55 56 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 57 }; |
58 class CP0TLB : public MipsStaticInst 59 { 60 protected: |
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51 | 61 |
62 /// Constructor 63 CP0TLB(const char *mnem, MachInst _machInst, OpClass __opClass) : 64 MipsStaticInst(mnem, _machInst, __opClass) 65 { 66 } 67 68 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 69 }; 70 71 |
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52 class CP1Control : public MipsStaticInst 53 { 54 protected: 55 56 /// Constructor 57 CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) : 58 MipsStaticInst(mnem, _machInst, __opClass) 59 { 60 } 61 62 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 63 }; 64 65}}; 66 67// Basic instruction class execute method template. | 72 class CP1Control : public MipsStaticInst 73 { 74 protected: 75 76 /// Constructor 77 CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) : 78 MipsStaticInst(mnem, _machInst, __opClass) 79 { 80 } 81 82 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 83 }; 84 85}}; 86 87// Basic instruction class execute method template. |
68def template ControlExecute {{ | 88def template CP0Execute {{ |
69 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 70 { 71 Fault fault = NoFault; 72 %(op_decl)s; 73 %(op_rd)s; 74 75 if (isCoprocessorEnabled(xc, 0)) { 76 %(code)s; 77 } else { | 89 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 90 { 91 Fault fault = NoFault; 92 %(op_decl)s; 93 %(op_rd)s; 94 95 if (isCoprocessorEnabled(xc, 0)) { 96 %(code)s; 97 } else { |
78 fault = new CoprocessorUnusableFault(); | 98 fault = new CoprocessorUnusableFault(0); |
79 } 80 81 if(fault == NoFault) 82 { 83 %(op_wb)s; 84 } 85 return fault; 86 } 87}}; 88 | 99 } 100 101 if(fault == NoFault) 102 { 103 %(op_wb)s; 104 } 105 return fault; 106 } 107}}; 108 |
109def template CP1Execute {{ 110 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 111 { 112 Fault fault = NoFault; 113 %(op_decl)s; 114 %(op_rd)s; 115 116 if (isCoprocessorEnabled(xc, 1)) { 117 %(code)s; 118 } else { 119 fault = new CoprocessorUnusableFault(1); 120 } 121 122 if(fault == NoFault) 123 { 124 %(op_wb)s; 125 } 126 return fault; 127 } 128}}; 129// Basic instruction class execute method template. 130def template ControlTLBExecute {{ 131 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 132 { 133 Fault fault = NoFault; 134 %(op_decl)s; 135 %(op_rd)s; 136 137#if FULL_SYSTEM 138 if (isCoprocessor0Enabled(xc)) { 139 if(isMMUTLB(xc)){ 140 %(code)s; 141 } else { 142 fault = new ReservedInstructionFault(); 143 } 144 } else { 145 fault = new CoprocessorUnusableFault(0); 146 } 147#else // Syscall Emulation Mode - No TLB Instructions 148 fault = new ReservedInstructionFault(); 149#endif 150 151 if(fault == NoFault) 152 { 153 %(op_wb)s; 154 } 155 return fault; 156 157 } 158}}; 159 |
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89//Outputs to decoder.cc 90output decoder {{ 91 std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const 92 { 93 std::stringstream ss; 94 ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL); 95 return ss.str(); 96 } | 160//Outputs to decoder.cc 161output decoder {{ 162 std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const 163 { 164 std::stringstream ss; 165 ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL); 166 return ss.str(); 167 } |
97 | 168 std::string CP0TLB::generateDisassembly(Addr pc, const SymbolTable *symtab) const 169 { 170 std::stringstream ss; 171 ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL); 172 return ss.str(); 173 } |
98 std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const 99 { 100 std::stringstream ss; 101 ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS); 102 return ss.str(); 103 } 104 105}}; 106 107output exec {{ 108 bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num) 109 { | 174 std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const 175 { 176 std::stringstream ss; 177 ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS); 178 return ss.str(); 179 } 180 181}}; 182 183output exec {{ 184 bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num) 185 { |
186 MiscReg Stat = xc->readMiscReg(MipsISA::Status); |
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110 switch(cop_num) 111 { 112 case 0: | 187 switch(cop_num) 188 { 189 case 0: |
190 { |
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113#if FULL_SYSTEM | 191#if FULL_SYSTEM |
114 if((xc->readMiscReg(MipsISA::Status) & 0x10000006) == 0 && (xc->readMiscReg(MipsISA::Debug) & 0x40000000 ) == 0) { 115 // Unable to use Status_CU0, etc directly, using bitfields & masks | 192 MiscReg Dbg = xc->readMiscReg(MipsISA::Debug); 193 if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible 194 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible 195 && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode 196 // Unable to use Status_CU0, etc directly, using bitfields & masks |
116 return false; 117 } 118#else 119 //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n"); 120#endif | 197 return false; 198 } 199#else 200 //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n"); 201#endif |
202 } |
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121 break; 122 case 1: | 203 break; 204 case 1: |
205 if((Stat & 0x20000000) == 0) // CU1 is reset 206 return false; |
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123 break; 124 case 2: | 207 break; 208 case 2: |
209 if((Stat & 0x40000000) == 0) // CU2 is reset 210 return false; |
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125 break; 126 case 3: | 211 break; 212 case 3: |
213 if((Stat & 0x80000000) == 0) // CU3 is reset 214 return false; |
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127 break; 128 default: panic("Invalid Coprocessor Number Specified"); 129 break; 130 } 131 return true; 132 } | 215 break; 216 default: panic("Invalid Coprocessor Number Specified"); 217 break; 218 } 219 return true; 220 } |
221 bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc) 222 { 223#if FULL_SYSTEM 224 MiscReg Stat = xc->readMiscRegNoEffect(MipsISA::Status); 225 MiscReg Dbg = xc->readMiscRegNoEffect(MipsISA::Debug); 226 if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible 227 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible 228 && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode 229 // Unable to use Status_CU0, etc directly, using bitfields & masks 230 return false; 231 } 232#else 233 //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n"); 234#endif 235 return true; 236 } 237 bool isMMUTLB(%(CPU_exec_context)s *xc) 238 { 239#if FULL_SYSTEM 240 if((xc->readMiscRegNoEffect(MipsISA::Config) & 0x00000380)==0x80) 241 return true; 242#endif 243 return false; 244 } |
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133}}; 134 135def format CP0Control(code, *flags) {{ 136 flags += ('IsNonSpeculative', ) 137 iop = InstObjParams(name, Name, 'CP0Control', code, flags) 138 header_output = BasicDeclare.subst(iop) 139 decoder_output = BasicConstructor.subst(iop) 140 decode_block = BasicDecode.subst(iop) | 245}}; 246 247def format CP0Control(code, *flags) {{ 248 flags += ('IsNonSpeculative', ) 249 iop = InstObjParams(name, Name, 'CP0Control', code, flags) 250 header_output = BasicDeclare.subst(iop) 251 decoder_output = BasicConstructor.subst(iop) 252 decode_block = BasicDecode.subst(iop) |
141 exec_output = ControlExecute.subst(iop) | 253 exec_output = CP0Execute.subst(iop) |
142}}; | 254}}; |
143 | 255def format CP0TLB(code, *flags) {{ 256 flags += ('IsNonSpeculative', ) 257 iop = InstObjParams(name, Name, 'CP0Control', code, flags) 258 header_output = BasicDeclare.subst(iop) 259 decoder_output = BasicConstructor.subst(iop) 260 decode_block = BasicDecode.subst(iop) 261 exec_output = ControlTLBExecute.subst(iop) 262}}; |
144def format CP1Control(code, *flags) {{ 145 flags += ('IsNonSpeculative', ) 146 iop = InstObjParams(name, Name, 'CP1Control', code, flags) 147 header_output = BasicDeclare.subst(iop) 148 decoder_output = BasicConstructor.subst(iop) 149 decode_block = BasicDecode.subst(iop) | 263def format CP1Control(code, *flags) {{ 264 flags += ('IsNonSpeculative', ) 265 iop = InstObjParams(name, Name, 'CP1Control', code, flags) 266 header_output = BasicDeclare.subst(iop) 267 decoder_output = BasicConstructor.subst(iop) 268 decode_block = BasicDecode.subst(iop) |
150 exec_output = ControlExecute.subst(iop) | 269 exec_output = CP1Execute.subst(iop) |
151}}; 152 153 | 270}}; 271 272 |