control.isa (12616:4b463b4dc098) control.isa (13615:5cc9363f5ab7)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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187
188output exec {{
189 bool
190 isCoprocessorEnabled(ExecContext *xc, unsigned cop_num)
191 {
192 if (!FullSystem)
193 return true;
194
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 178 unchanged lines hidden (view full) ---

187
188output exec {{
189 bool
190 isCoprocessorEnabled(ExecContext *xc, unsigned cop_num)
191 {
192 if (!FullSystem)
193 return true;
194
195 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
195 RegVal Stat = xc->readMiscReg(MISCREG_STATUS);
196 if (cop_num == 0) {
196 if (cop_num == 0) {
197 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
197 RegVal Dbg = xc->readMiscReg(MISCREG_DEBUG);
198 // In Stat, EXL, ERL or CU0 set, CP0 accessible
199 // In Dbg, DM bit set, CP0 accessible
200 // In Stat, KSU = 0, kernel mode is base mode
201 return (Stat & 0x10000006) ||
202 (Dbg & 0x40000000) ||
203 !(Stat & 0x00000018);
204 } else if (cop_num < 4) {
205 return Stat & (0x10000000 << cop_num); // CU is reset
206 } else {
207 panic("Invalid Coprocessor Number Specified");
208 }
209 }
210
211 bool inline
212 isCoprocessor0Enabled(ExecContext *xc)
213 {
214 if (FullSystem) {
198 // In Stat, EXL, ERL or CU0 set, CP0 accessible
199 // In Dbg, DM bit set, CP0 accessible
200 // In Stat, KSU = 0, kernel mode is base mode
201 return (Stat & 0x10000006) ||
202 (Dbg & 0x40000000) ||
203 !(Stat & 0x00000018);
204 } else if (cop_num < 4) {
205 return Stat & (0x10000000 << cop_num); // CU is reset
206 } else {
207 panic("Invalid Coprocessor Number Specified");
208 }
209 }
210
211 bool inline
212 isCoprocessor0Enabled(ExecContext *xc)
213 {
214 if (FullSystem) {
215 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
216 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
215 RegVal Stat = xc->readMiscReg(MISCREG_STATUS);
216 RegVal Dbg = xc->readMiscReg(MISCREG_DEBUG);
217 // In Stat, EXL, ERL or CU0 set, CP0 accessible
218 // In Dbg, DM bit set, CP0 accessible
219 // In Stat KSU = 0, kernel mode is base mode
220 return (Stat & 0x10000006) || (Dbg & 0x40000000) ||
221 !(Stat & 0x00000018);
222 } else {
223 return true;
224 }
225 }
226
227 bool
228 isMMUTLB(ExecContext *xc)
229 {
217 // In Stat, EXL, ERL or CU0 set, CP0 accessible
218 // In Dbg, DM bit set, CP0 accessible
219 // In Stat KSU = 0, kernel mode is base mode
220 return (Stat & 0x10000006) || (Dbg & 0x40000000) ||
221 !(Stat & 0x00000018);
222 } else {
223 return true;
224 }
225 }
226
227 bool
228 isMMUTLB(ExecContext *xc)
229 {
230 MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
230 RegVal Config = xc->readMiscReg(MISCREG_CONFIG);
231 return FullSystem && (Config & 0x380) == 0x80;
232 }
233}};
234
235def format CP0Control(code, *flags) {{
236 flags += ('IsNonSpeculative', )
237 iop = InstObjParams(name, Name, 'CP0Control', code, flags)
238 header_output = BasicDeclare.subst(iop)

--- 22 unchanged lines hidden --- 		231 return FullSystem && (Config & 0x380) == 0x80;
232 }
233}};
234
235def format CP0Control(code, *flags) {{
236 flags += ('IsNonSpeculative', )
237 iop = InstObjParams(name, Name, 'CP0Control', code, flags)
238 header_output = BasicDeclare.subst(iop)

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