control.isa (10474:799c8ee4ecba) control.isa (12234:78ece221f9f5)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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75
76 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
77 };
78
79}};
80
81// Basic instruction class execute method template.
82def template CP0Execute {{
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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75
76 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
77 };
78
79}};
80
81// Basic instruction class execute method template.
82def template CP0Execute {{
83 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
83 Fault %(class_name)s::execute(
84 ExecContext *xc, Trace::InstRecord *traceData) const
84 {
85 Fault fault = NoFault;
86 %(op_decl)s;
87 %(op_rd)s;
88
89 if (isCoprocessorEnabled(xc, 0)) {
90 %(code)s;
91

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96 } else {
97 fault = std::make_shared<CoprocessorUnusableFault>(0);
98 }
99 return fault;
100 }
101}};
102
103def template CP1Execute {{
85 {
86 Fault fault = NoFault;
87 %(op_decl)s;
88 %(op_rd)s;
89
90 if (isCoprocessorEnabled(xc, 0)) {
91 %(code)s;
92

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97 } else {
98 fault = std::make_shared<CoprocessorUnusableFault>(0);
99 }
100 return fault;
101 }
102}};
103
104def template CP1Execute {{
104 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
105 Fault %(class_name)s::execute(
106 ExecContext *xc, Trace::InstRecord *traceData) const
105 {
106 Fault fault = NoFault;
107 %(op_decl)s;
108 %(op_rd)s;
109
110 if (isCoprocessorEnabled(xc, 1)) {
111 %(code)s;
112 } else {

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117 {
118 %(op_wb)s;
119 }
120 return fault;
121 }
122}};
123// Basic instruction class execute method template.
124def template ControlTLBExecute {{
107 {
108 Fault fault = NoFault;
109 %(op_decl)s;
110 %(op_rd)s;
111
112 if (isCoprocessorEnabled(xc, 1)) {
113 %(code)s;
114 } else {

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119 {
120 %(op_wb)s;
121 }
122 return fault;
123 }
124}};
125// Basic instruction class execute method template.
126def template ControlTLBExecute {{
125 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
127 Fault %(class_name)s::execute(
128 ExecContext *xc, Trace::InstRecord *traceData) const
126 {
127 Fault fault = NoFault;
128 %(op_decl)s;
129 %(op_rd)s;
130
131 if (FullSystem) {
132 if (isCoprocessor0Enabled(xc)) {
133 if(isMMUTLB(xc)){

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168 std::stringstream ss;
169 ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
170 return ss.str();
171 }
172
173}};
174
175output header {{
129 {
130 Fault fault = NoFault;
131 %(op_decl)s;
132 %(op_rd)s;
133
134 if (FullSystem) {
135 if (isCoprocessor0Enabled(xc)) {
136 if(isMMUTLB(xc)){

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171 std::stringstream ss;
172 ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
173 return ss.str();
174 }
175
176}};
177
178output header {{
176 bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num);
179 bool isCoprocessorEnabled(ExecContext *xc, unsigned cop_num);
177
180
178 bool isMMUTLB(%(CPU_exec_context)s *xc);
181 bool isMMUTLB(ExecContext *xc);
179
180}};
181
182output exec {{
183 bool
182
183}};
184
185output exec {{
186 bool
184 isCoprocessorEnabled(CPU_EXEC_CONTEXT *xc, unsigned cop_num)
187 isCoprocessorEnabled(ExecContext *xc, unsigned cop_num)
185 {
186 if (!FullSystem)
187 return true;
188
189 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
190 if (cop_num == 0) {
191 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
192 // In Stat, EXL, ERL or CU0 set, CP0 accessible

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198 } else if (cop_num < 4) {
199 return Stat & (0x10000000 << cop_num); // CU is reset
200 } else {
201 panic("Invalid Coprocessor Number Specified");
202 }
203 }
204
205 bool inline
188 {
189 if (!FullSystem)
190 return true;
191
192 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
193 if (cop_num == 0) {
194 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
195 // In Stat, EXL, ERL or CU0 set, CP0 accessible

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201 } else if (cop_num < 4) {
202 return Stat & (0x10000000 << cop_num); // CU is reset
203 } else {
204 panic("Invalid Coprocessor Number Specified");
205 }
206 }
207
208 bool inline
206 isCoprocessor0Enabled(CPU_EXEC_CONTEXT *xc)
209 isCoprocessor0Enabled(ExecContext *xc)
207 {
208 if (FullSystem) {
209 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
210 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
211 // In Stat, EXL, ERL or CU0 set, CP0 accessible
212 // In Dbg, DM bit set, CP0 accessible
213 // In Stat KSU = 0, kernel mode is base mode
214 return (Stat & 0x10000006) || (Dbg & 0x40000000) ||
215 !(Stat & 0x00000018);
216 } else {
217 return true;
218 }
219 }
220
221 bool
210 {
211 if (FullSystem) {
212 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
213 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
214 // In Stat, EXL, ERL or CU0 set, CP0 accessible
215 // In Dbg, DM bit set, CP0 accessible
216 // In Stat KSU = 0, kernel mode is base mode
217 return (Stat & 0x10000006) || (Dbg & 0x40000000) ||
218 !(Stat & 0x00000018);
219 } else {
220 return true;
221 }
222 }
223
224 bool
222 isMMUTLB(CPU_EXEC_CONTEXT *xc)
225 isMMUTLB(ExecContext *xc)
223 {
224 MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
225 return FullSystem && (Config & 0x380) == 0x80;
226 }
227}};
228
229def format CP0Control(code, *flags) {{
230 flags += ('IsNonSpeculative', )

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227 MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
228 return FullSystem && (Config & 0x380) == 0x80;
229 }
230}};
231
232def format CP0Control(code, *flags) {{
233 flags += ('IsNonSpeculative', )

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