1// -*- mode:c++ -*- 2 3// Copyright (c) 2006 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell 30 31//////////////////////////////////////////////////////////////////// 32//
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33// Integer operate instructions
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33// Coprocessor instructions |
34// 35 36//Outputs to decoder.hh 37output header {{ 38
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39 class Control : public MipsStaticInst
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39 class CP0Control : public MipsStaticInst |
40 { 41 protected: 42 43 /// Constructor
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44 Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
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44 CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) : |
45 MipsStaticInst(mnem, _machInst, __opClass) 46 { 47 } 48 49 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 50 }; 51
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52 class CP0Control : public Control
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52 class CP1Control : public MipsStaticInst |
53 { 54 protected: 55 56 /// Constructor
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57 CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
58 Control(mnem, _machInst, __opClass)
59 {
60 }
61
62 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
63 };
64
65 class CP1Control : public Control
66 {
67 protected:
68
69 /// Constructor
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57 CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
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71 Control(mnem, _machInst, __opClass)
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58 MipsStaticInst(mnem, _machInst, __opClass) |
59 { 60 } 61 62 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 63 }; 64 65}}; 66
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80//Outputs to decoder.cc
81output decoder {{
82 std::string Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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67// Basic instruction class execute method template. 68def template ControlExecute {{ 69 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const |
70 {
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84 std::stringstream ss;
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71 Fault fault = NoFault; 72 %(op_decl)s; 73 %(op_rd)s; |
74
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86 ccprintf(ss, "%-10s ", mnemonic);
87
88 if (mnemonic == "mfc0" || mnemonic == "mtc0") {
89 ccprintf(ss, "%-10s %d,%d,%d", mnemonic,RT,RD,SEL);
90 } else {
91
92 // just print the first dest... if there's a second one,
93 // it's generally implicit
94 if (_numDestRegs > 0) {
95 printReg(ss, _destRegIdx[0]);
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75 if (isCoprocessorEnabled(xc, 0)) { 76 %(code)s; 77 } else { 78 fault = new CoprocessorUnusableFault(); |
79 } 80
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98 ss << ", ";
99
100 // just print the first two source regs... if there's
101 // a third one, it's a read-modify-write dest (Rc),
102 // e.g. for CMOVxx
103 if (_numSrcRegs > 0) {
104 printReg(ss, _srcRegIdx[0]);
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81 if(fault == NoFault) 82 { 83 %(op_wb)s; |
84 }
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106
107 if (_numSrcRegs > 1) {
108 ss << ", ";
109 printReg(ss, _srcRegIdx[1]);
110 }
111 }
112
113 return ss.str();
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85 return fault; |
86 }
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87}}; |
88
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89//Outputs to decoder.cc 90output decoder {{ |
91 std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const 92 { 93 std::stringstream ss;
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119 ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
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94 ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL); |
95 return ss.str(); 96 } 97 98 std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const 99 { 100 std::stringstream ss; 101 ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS); 102 return ss.str(); 103 } 104 105}}; 106
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132def format System(code, *flags) {{
133 iop = InstObjParams(name, Name, 'Control', code, flags)
134 header_output = BasicDeclare.subst(iop)
135 decoder_output = BasicConstructor.subst(iop)
136 decode_block = BasicDecode.subst(iop)
137 exec_output = BasicExecute.subst(iop)
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107output exec {{ 108 bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num) 109 { 110 switch(cop_num) 111 { 112 case 0: 113#if FULL_SYSTEM 114 if((xc->readMiscReg(MipsISA::Status) & 0x10000006) == 0 && (xc->readMiscReg(MipsISA::Debug) & 0x40000000 ) == 0) { 115 // Unable to use Status_CU0, etc directly, using bitfields & masks 116 return false; 117 } 118#else 119 //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n"); 120#endif 121 break; 122 case 1: 123 break; 124 case 2: 125 break; 126 case 3: 127 break; 128 default: panic("Invalid Coprocessor Number Specified"); 129 break; 130 } 131 return true; 132 } |
133}}; 134 135def format CP0Control(code, *flags) {{
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141 iop = InstObjParams(name, Name, 'CP0Control', code, flags)
142 header_output = BasicDeclare.subst(iop)
143 decoder_output = BasicConstructor.subst(iop)
144 decode_block = BasicDecode.subst(iop)
145 exec_output = BasicExecute.subst(iop)
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136 flags += ('IsNonSpeculative', ) 137 iop = InstObjParams(name, Name, 'CP0Control', code, flags) 138 header_output = BasicDeclare.subst(iop) 139 decoder_output = BasicConstructor.subst(iop) 140 decode_block = BasicDecode.subst(iop) 141 exec_output = ControlExecute.subst(iop) |
142}}; 143 144def format CP1Control(code, *flags) {{
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149 iop = InstObjParams(name, Name, 'CP1Control', code, flags)
150 header_output = BasicDeclare.subst(iop)
151 decoder_output = BasicConstructor.subst(iop)
152 decode_block = BasicDecode.subst(iop)
153 exec_output = BasicExecute.subst(iop)
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145 flags += ('IsNonSpeculative', ) 146 iop = InstObjParams(name, Name, 'CP1Control', code, flags) 147 header_output = BasicDeclare.subst(iop) 148 decoder_output = BasicConstructor.subst(iop) 149 decode_block = BasicDecode.subst(iop) 150 exec_output = ControlExecute.subst(iop) |
151}}; 152 153
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