1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 66 unchanged lines hidden (view full) --- 75 76 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 77 }; 78 79}}; 80 81// Basic instruction class execute method template. 82def template CP0Execute {{ |
83 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const |
84 { 85 Fault fault = NoFault; 86 %(op_decl)s; 87 %(op_rd)s; 88 89 if (isCoprocessorEnabled(xc, 0)) { 90 %(code)s; 91 --- 4 unchanged lines hidden (view full) --- 96 } else { 97 fault = new CoprocessorUnusableFault(0); 98 } 99 return fault; 100 } 101}}; 102 103def template CP1Execute {{ |
104 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const |
105 { 106 Fault fault = NoFault; 107 %(op_decl)s; 108 %(op_rd)s; 109 110 if (isCoprocessorEnabled(xc, 1)) { 111 %(code)s; 112 } else { --- 4 unchanged lines hidden (view full) --- 117 { 118 %(op_wb)s; 119 } 120 return fault; 121 } 122}}; 123// Basic instruction class execute method template. 124def template ControlTLBExecute {{ |
125 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const |
126 { 127 Fault fault = NoFault; 128 %(op_decl)s; 129 %(op_rd)s; 130 131 if (FullSystem) { 132 if (isCoprocessor0Enabled(xc)) { 133 if(isMMUTLB(xc)){ --- 42 unchanged lines hidden (view full) --- 176 bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num); 177 178 bool isMMUTLB(%(CPU_exec_context)s *xc); 179 180}}; 181 182output exec {{ 183 bool |
184 isCoprocessorEnabled(CPU_EXEC_CONTEXT *xc, unsigned cop_num) |
185 { 186 if (!FullSystem) 187 return true; 188 189 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS); 190 if (cop_num == 0) { 191 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG); 192 // In Stat, EXL, ERL or CU0 set, CP0 accessible --- 5 unchanged lines hidden (view full) --- 198 } else if (cop_num < 4) { 199 return Stat & (0x10000000 << cop_num); // CU is reset 200 } else { 201 panic("Invalid Coprocessor Number Specified"); 202 } 203 } 204 205 bool inline |
206 isCoprocessor0Enabled(CPU_EXEC_CONTEXT *xc) |
207 { 208 if (FullSystem) { 209 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS); 210 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG); 211 // In Stat, EXL, ERL or CU0 set, CP0 accessible 212 // In Dbg, DM bit set, CP0 accessible 213 // In Stat KSU = 0, kernel mode is base mode 214 return (Stat & 0x10000006) || (Dbg & 0x40000000) || 215 !(Stat & 0x00000018); 216 } else { 217 return true; 218 } 219 } 220 221 bool |
222 isMMUTLB(CPU_EXEC_CONTEXT *xc) |
223 { 224 MiscReg Config = xc->readMiscReg(MISCREG_CONFIG); 225 return FullSystem && (Config & 0x380) == 0x80; 226 } 227}}; 228 229def format CP0Control(code, *flags) {{ 230 flags += ('IsNonSpeculative', ) --- 24 unchanged lines hidden --- |