127,129c127,129
< Fault fault = NoFault;
< %(op_decl)s;
< %(op_rd)s;
---
> Fault fault = NoFault;
> %(op_decl)s;
> %(op_rd)s;
131c131
< #if FULL_SYSTEM
---
> if (FULL_SYSTEM) {
133,137c133,137
< if(isMMUTLB(xc)){
< %(code)s;
< } else {
< fault = new ReservedInstructionFault();
< }
---
> if(isMMUTLB(xc)){
> %(code)s;
> } else {
> fault = new ReservedInstructionFault();
> }
139c139
< fault = new CoprocessorUnusableFault(0);
---
> fault = new CoprocessorUnusableFault(0);
141c141
< #else // Syscall Emulation Mode - No TLB Instructions
---
> } else { // Syscall Emulation Mode - No TLB Instructions
143c143
< #endif
---
> }
145,150c145,148
< if(fault == NoFault)
< {
< %(op_wb)s;
< }
< return fault;
<
---
> if (fault == NoFault) {
> %(op_wb)s;
> }
> return fault;
178c176,177
< bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
---
> bool
> isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
180,194c179,180
< #if !FULL_SYSTEM
< return true;
< #else
< MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
< switch(cop_num)
< {
< case 0:
< {
< MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
< if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
< && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
< && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
< // Unable to use Status_CU0, etc directly, using bitfields & masks
< return false;
< }
---
> if (!FULL_SYSTEM)
> return true;
196,211c182,194
< }
< break;
< case 1:
< if((Stat & 0x20000000) == 0) // CU1 is reset
< return false;
< break;
< case 2:
< if((Stat & 0x40000000) == 0) // CU2 is reset
< return false;
< break;
< case 3:
< if((Stat & 0x80000000) == 0) // CU3 is reset
< return false;
< break;
< default: panic("Invalid Coprocessor Number Specified");
< break;
---
> MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
> if (cop_num == 0) {
> MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
> // In Stat, EXL, ERL or CU0 set, CP0 accessible
> // In Dbg, DM bit set, CP0 accessible
> // In Stat, KSU = 0, kernel mode is base mode
> return (Stat & 0x10000006) ||
> (Dbg & 0x40000000) ||
> !(Stat & 0x00000018);
> } else if (cop_num < 4) {
> return Stat & (0x10000000 << cop_num); // CU is reset
> } else {
> panic("Invalid Coprocessor Number Specified");
213,214d195
< return true;
< #endif
216c197,199
< bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
---
>
> bool inline
> isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
218,230c201,211
< #if FULL_SYSTEM
< MiscReg Stat = xc->readMiscRegNoEffect(MISCREG_STATUS);
< MiscReg Dbg = xc->readMiscRegNoEffect(MISCREG_DEBUG);
< if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
< && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
< && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
< // Unable to use Status_CU0, etc directly, using bitfields & masks
< return false;
< }
< #else
< //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
< #endif
< return true;
---
> if (FULL_SYSTEM) {
> MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
> MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
> // In Stat, EXL, ERL or CU0 set, CP0 accessible
> // In Dbg, DM bit set, CP0 accessible
> // In Stat KSU = 0, kernel mode is base mode
> return (Stat & 0x10000006) || (Dbg & 0x40000000) ||
> !(Stat & 0x00000018);
> } else {
> return true;
> }
232c213,215
< bool isMMUTLB(%(CPU_exec_context)s *xc)
---
>
> bool
> isMMUTLB(%(CPU_exec_context)s *xc)
234,238c217,218
< #if FULL_SYSTEM
< if((xc->readMiscRegNoEffect(MISCREG_CONFIG) & 0x00000380)==0x80)
< return true;
< #endif
< return false;
---
> MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
> return FULL_SYSTEM && (Config & 0x380) == 0x80;