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< // Integer operate instructions
---
> // Coprocessor instructions
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< class Control : public MipsStaticInst
---
> class CP0Control : public MipsStaticInst
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< Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
---
> CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
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< class CP0Control : public Control
---
> class CP1Control : public MipsStaticInst
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< CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
< Control(mnem, _machInst, __opClass)
< {
< }
<
< std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
< };
<
< class CP1Control : public Control
< {
< protected:
<
< /// Constructor
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< Control(mnem, _machInst, __opClass)
---
> MipsStaticInst(mnem, _machInst, __opClass)
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< //Outputs to decoder.cc
< output decoder {{
< std::string Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
---
> // Basic instruction class execute method template.
> def template ControlExecute {{
> Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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< std::stringstream ss;
---
> Fault fault = NoFault;
> %(op_decl)s;
> %(op_rd)s;
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< ccprintf(ss, "%-10s ", mnemonic);
<
< if (mnemonic == "mfc0" || mnemonic == "mtc0") {
< ccprintf(ss, "%-10s %d,%d,%d", mnemonic,RT,RD,SEL);
< } else {
<
< // just print the first dest... if there's a second one,
< // it's generally implicit
< if (_numDestRegs > 0) {
< printReg(ss, _destRegIdx[0]);
---
> if (isCoprocessorEnabled(xc, 0)) {
> %(code)s;
> } else {
> fault = new CoprocessorUnusableFault();
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< ss << ", ";
<
< // just print the first two source regs... if there's
< // a third one, it's a read-modify-write dest (Rc),
< // e.g. for CMOVxx
< if (_numSrcRegs > 0) {
< printReg(ss, _srcRegIdx[0]);
---
> if(fault == NoFault)
> {
> %(op_wb)s;
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<
< if (_numSrcRegs > 1) {
< ss << ", ";
< printReg(ss, _srcRegIdx[1]);
< }
< }
<
< return ss.str();
---
> return fault;
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> }};
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> //Outputs to decoder.cc
> output decoder {{
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< ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
---
> ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
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< def format System(code, *flags) {{
< iop = InstObjParams(name, Name, 'Control', code, flags)
< header_output = BasicDeclare.subst(iop)
< decoder_output = BasicConstructor.subst(iop)
< decode_block = BasicDecode.subst(iop)
< exec_output = BasicExecute.subst(iop)
---
> output exec {{
> bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
> {
> switch(cop_num)
> {
> case 0:
> #if FULL_SYSTEM
> if((xc->readMiscReg(MipsISA::Status) & 0x10000006) == 0 && (xc->readMiscReg(MipsISA::Debug) & 0x40000000 ) == 0) {
> // Unable to use Status_CU0, etc directly, using bitfields & masks
> return false;
> }
> #else
> //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
> #endif
> break;
> case 1:
> break;
> case 2:
> break;
> case 3:
> break;
> default: panic("Invalid Coprocessor Number Specified");
> break;
> }
> return true;
> }
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< iop = InstObjParams(name, Name, 'CP0Control', code, flags)
< header_output = BasicDeclare.subst(iop)
< decoder_output = BasicConstructor.subst(iop)
< decode_block = BasicDecode.subst(iop)
< exec_output = BasicExecute.subst(iop)
---
> flags += ('IsNonSpeculative', )
> iop = InstObjParams(name, Name, 'CP0Control', code, flags)
> header_output = BasicDeclare.subst(iop)
> decoder_output = BasicConstructor.subst(iop)
> decode_block = BasicDecode.subst(iop)
> exec_output = ControlExecute.subst(iop)
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< iop = InstObjParams(name, Name, 'CP1Control', code, flags)
< header_output = BasicDeclare.subst(iop)
< decoder_output = BasicConstructor.subst(iop)
< decode_block = BasicDecode.subst(iop)
< exec_output = BasicExecute.subst(iop)
---
> flags += ('IsNonSpeculative', )
> iop = InstObjParams(name, Name, 'CP1Control', code, flags)
> header_output = BasicDeclare.subst(iop)
> decoder_output = BasicConstructor.subst(iop)
> decode_block = BasicDecode.subst(iop)
> exec_output = ControlExecute.subst(iop)