1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30// Jaidev Patwardhan
31
32////////////////////////////////////////////////////////////////////
33//
34// Coprocessor instructions
35//
36
37//Outputs to decoder.hh
38output header {{
39
40 class CP0Control : public MipsStaticInst
41 {
42 protected:
43
44 /// Constructor
45 CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
46 MipsStaticInst(mnem, _machInst, __opClass)
47 {
48 }
49
50 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
51 };
52 class CP0TLB : public MipsStaticInst
53 {
54 protected:
55
56 /// Constructor
57 CP0TLB(const char *mnem, MachInst _machInst, OpClass __opClass) :
58 MipsStaticInst(mnem, _machInst, __opClass)
59 {
60 }
61
62 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
63 };
64
65
66 class CP1Control : public MipsStaticInst
67 {
68 protected:
69
70 /// Constructor
71 CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
72 MipsStaticInst(mnem, _machInst, __opClass)
73 {
74 }
75
76 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
77 };
78
79}};
80
81// Basic instruction class execute method template.
82def template CP0Execute {{
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30// Jaidev Patwardhan
31
32////////////////////////////////////////////////////////////////////
33//
34// Coprocessor instructions
35//
36
37//Outputs to decoder.hh
38output header {{
39
40 class CP0Control : public MipsStaticInst
41 {
42 protected:
43
44 /// Constructor
45 CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
46 MipsStaticInst(mnem, _machInst, __opClass)
47 {
48 }
49
50 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
51 };
52 class CP0TLB : public MipsStaticInst
53 {
54 protected:
55
56 /// Constructor
57 CP0TLB(const char *mnem, MachInst _machInst, OpClass __opClass) :
58 MipsStaticInst(mnem, _machInst, __opClass)
59 {
60 }
61
62 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
63 };
64
65
66 class CP1Control : public MipsStaticInst
67 {
68 protected:
69
70 /// Constructor
71 CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
72 MipsStaticInst(mnem, _machInst, __opClass)
73 {
74 }
75
76 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
77 };
78
79}};
80
81// Basic instruction class execute method template.
82def template CP0Execute {{
|
83 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
| 83 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
|
84 {
85 Fault fault = NoFault;
86 %(op_decl)s;
87 %(op_rd)s;
88
89 if (isCoprocessorEnabled(xc, 0)) {
90 %(code)s;
91
92 if(fault == NoFault)
93 {
94 %(op_wb)s;
95 }
96 } else {
97 fault = new CoprocessorUnusableFault(0);
98 }
99 return fault;
100 }
101}};
102
103def template CP1Execute {{
| 84 {
85 Fault fault = NoFault;
86 %(op_decl)s;
87 %(op_rd)s;
88
89 if (isCoprocessorEnabled(xc, 0)) {
90 %(code)s;
91
92 if(fault == NoFault)
93 {
94 %(op_wb)s;
95 }
96 } else {
97 fault = new CoprocessorUnusableFault(0);
98 }
99 return fault;
100 }
101}};
102
103def template CP1Execute {{
|
104 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
| 104 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
|
105 {
106 Fault fault = NoFault;
107 %(op_decl)s;
108 %(op_rd)s;
109
110 if (isCoprocessorEnabled(xc, 1)) {
111 %(code)s;
112 } else {
113 fault = new CoprocessorUnusableFault(1);
114 }
115
116 if(fault == NoFault)
117 {
118 %(op_wb)s;
119 }
120 return fault;
121 }
122}};
123// Basic instruction class execute method template.
124def template ControlTLBExecute {{
| 105 {
106 Fault fault = NoFault;
107 %(op_decl)s;
108 %(op_rd)s;
109
110 if (isCoprocessorEnabled(xc, 1)) {
111 %(code)s;
112 } else {
113 fault = new CoprocessorUnusableFault(1);
114 }
115
116 if(fault == NoFault)
117 {
118 %(op_wb)s;
119 }
120 return fault;
121 }
122}};
123// Basic instruction class execute method template.
124def template ControlTLBExecute {{
|
125 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
| 125 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
|
126 {
127 Fault fault = NoFault;
128 %(op_decl)s;
129 %(op_rd)s;
130
131 if (FullSystem) {
132 if (isCoprocessor0Enabled(xc)) {
133 if(isMMUTLB(xc)){
134 %(code)s;
135 } else {
136 fault = new ReservedInstructionFault();
137 }
138 } else {
139 fault = new CoprocessorUnusableFault(0);
140 }
141 } else { // Syscall Emulation Mode - No TLB Instructions
142 fault = new ReservedInstructionFault();
143 }
144
145 if (fault == NoFault) {
146 %(op_wb)s;
147 }
148 return fault;
149 }
150}};
151
152//Outputs to decoder.cc
153output decoder {{
154 std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
155 {
156 std::stringstream ss;
157 ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
158 return ss.str();
159 }
160 std::string CP0TLB::generateDisassembly(Addr pc, const SymbolTable *symtab) const
161 {
162 std::stringstream ss;
163 ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
164 return ss.str();
165 }
166 std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
167 {
168 std::stringstream ss;
169 ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
170 return ss.str();
171 }
172
173}};
174
175output header {{
176 bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num);
177
178 bool isMMUTLB(%(CPU_exec_context)s *xc);
179
180}};
181
182output exec {{
183 bool
| 126 {
127 Fault fault = NoFault;
128 %(op_decl)s;
129 %(op_rd)s;
130
131 if (FullSystem) {
132 if (isCoprocessor0Enabled(xc)) {
133 if(isMMUTLB(xc)){
134 %(code)s;
135 } else {
136 fault = new ReservedInstructionFault();
137 }
138 } else {
139 fault = new CoprocessorUnusableFault(0);
140 }
141 } else { // Syscall Emulation Mode - No TLB Instructions
142 fault = new ReservedInstructionFault();
143 }
144
145 if (fault == NoFault) {
146 %(op_wb)s;
147 }
148 return fault;
149 }
150}};
151
152//Outputs to decoder.cc
153output decoder {{
154 std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
155 {
156 std::stringstream ss;
157 ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
158 return ss.str();
159 }
160 std::string CP0TLB::generateDisassembly(Addr pc, const SymbolTable *symtab) const
161 {
162 std::stringstream ss;
163 ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
164 return ss.str();
165 }
166 std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
167 {
168 std::stringstream ss;
169 ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
170 return ss.str();
171 }
172
173}};
174
175output header {{
176 bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num);
177
178 bool isMMUTLB(%(CPU_exec_context)s *xc);
179
180}};
181
182output exec {{
183 bool
|
184 isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
| 184 isCoprocessorEnabled(CPU_EXEC_CONTEXT *xc, unsigned cop_num)
|
185 {
186 if (!FullSystem)
187 return true;
188
189 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
190 if (cop_num == 0) {
191 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
192 // In Stat, EXL, ERL or CU0 set, CP0 accessible
193 // In Dbg, DM bit set, CP0 accessible
194 // In Stat, KSU = 0, kernel mode is base mode
195 return (Stat & 0x10000006) ||
196 (Dbg & 0x40000000) ||
197 !(Stat & 0x00000018);
198 } else if (cop_num < 4) {
199 return Stat & (0x10000000 << cop_num); // CU is reset
200 } else {
201 panic("Invalid Coprocessor Number Specified");
202 }
203 }
204
205 bool inline
| 185 {
186 if (!FullSystem)
187 return true;
188
189 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
190 if (cop_num == 0) {
191 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
192 // In Stat, EXL, ERL or CU0 set, CP0 accessible
193 // In Dbg, DM bit set, CP0 accessible
194 // In Stat, KSU = 0, kernel mode is base mode
195 return (Stat & 0x10000006) ||
196 (Dbg & 0x40000000) ||
197 !(Stat & 0x00000018);
198 } else if (cop_num < 4) {
199 return Stat & (0x10000000 << cop_num); // CU is reset
200 } else {
201 panic("Invalid Coprocessor Number Specified");
202 }
203 }
204
205 bool inline
|
206 isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
| 206 isCoprocessor0Enabled(CPU_EXEC_CONTEXT *xc)
|
207 {
208 if (FullSystem) {
209 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
210 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
211 // In Stat, EXL, ERL or CU0 set, CP0 accessible
212 // In Dbg, DM bit set, CP0 accessible
213 // In Stat KSU = 0, kernel mode is base mode
214 return (Stat & 0x10000006) || (Dbg & 0x40000000) ||
215 !(Stat & 0x00000018);
216 } else {
217 return true;
218 }
219 }
220
221 bool
| 207 {
208 if (FullSystem) {
209 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
210 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
211 // In Stat, EXL, ERL or CU0 set, CP0 accessible
212 // In Dbg, DM bit set, CP0 accessible
213 // In Stat KSU = 0, kernel mode is base mode
214 return (Stat & 0x10000006) || (Dbg & 0x40000000) ||
215 !(Stat & 0x00000018);
216 } else {
217 return true;
218 }
219 }
220
221 bool
|
222 isMMUTLB(%(CPU_exec_context)s *xc)
| 222 isMMUTLB(CPU_EXEC_CONTEXT *xc)
|
223 {
224 MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
225 return FullSystem && (Config & 0x380) == 0x80;
226 }
227}};
228
229def format CP0Control(code, *flags) {{
230 flags += ('IsNonSpeculative', )
231 iop = InstObjParams(name, Name, 'CP0Control', code, flags)
232 header_output = BasicDeclare.subst(iop)
233 decoder_output = BasicConstructor.subst(iop)
234 decode_block = BasicDecode.subst(iop)
235 exec_output = CP0Execute.subst(iop)
236}};
237def format CP0TLB(code, *flags) {{
238 flags += ('IsNonSpeculative', )
239 iop = InstObjParams(name, Name, 'CP0Control', code, flags)
240 header_output = BasicDeclare.subst(iop)
241 decoder_output = BasicConstructor.subst(iop)
242 decode_block = BasicDecode.subst(iop)
243 exec_output = ControlTLBExecute.subst(iop)
244}};
245def format CP1Control(code, *flags) {{
246 flags += ('IsNonSpeculative', )
247 iop = InstObjParams(name, Name, 'CP1Control', code, flags)
248 header_output = BasicDeclare.subst(iop)
249 decoder_output = BasicConstructor.subst(iop)
250 decode_block = BasicDecode.subst(iop)
251 exec_output = CP1Execute.subst(iop)
252}};
253
254
| 223 {
224 MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
225 return FullSystem && (Config & 0x380) == 0x80;
226 }
227}};
228
229def format CP0Control(code, *flags) {{
230 flags += ('IsNonSpeculative', )
231 iop = InstObjParams(name, Name, 'CP0Control', code, flags)
232 header_output = BasicDeclare.subst(iop)
233 decoder_output = BasicConstructor.subst(iop)
234 decode_block = BasicDecode.subst(iop)
235 exec_output = CP0Execute.subst(iop)
236}};
237def format CP0TLB(code, *flags) {{
238 flags += ('IsNonSpeculative', )
239 iop = InstObjParams(name, Name, 'CP0Control', code, flags)
240 header_output = BasicDeclare.subst(iop)
241 decoder_output = BasicConstructor.subst(iop)
242 decode_block = BasicDecode.subst(iop)
243 exec_output = ControlTLBExecute.subst(iop)
244}};
245def format CP1Control(code, *flags) {{
246 flags += ('IsNonSpeculative', )
247 iop = InstObjParams(name, Name, 'CP1Control', code, flags)
248 header_output = BasicDeclare.subst(iop)
249 decoder_output = BasicConstructor.subst(iop)
250 decode_block = BasicDecode.subst(iop)
251 exec_output = CP1Execute.subst(iop)
252}};
253
254
|