control.isa (2686:f0d591379ac3) control.isa (2706:d88c27f75121)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30
3////////////////////////////////////////////////////////////////////
4//
5// Integer operate instructions
6//
7
8//Outputs to decoder.hh
9output header {{
10
11 class Control : public MipsStaticInst
12 {
13 protected:
14
15 /// Constructor
16 Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
17 MipsStaticInst(mnem, _machInst, __opClass)
18 {
19 }
20
21 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
22 };
23
24 class CP0Control : public Control
25 {
26 protected:
27
28 /// Constructor
29 CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
30 Control(mnem, _machInst, __opClass)
31 {
32 }
33
34 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
35 };
36
37 class CP1Control : public Control
38 {
39 protected:
40
41 /// Constructor
42 CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
43 Control(mnem, _machInst, __opClass)
44 {
45 }
46
47 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
48 };
49
50}};
51
52//Outputs to decoder.cc
53output decoder {{
54 std::string Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
55 {
56 std::stringstream ss;
57
58 ccprintf(ss, "%-10s ", mnemonic);
59
60 if (mnemonic == "mfc0" || mnemonic == "mtc0") {
61 ccprintf(ss, "%-10s %d,%d,%d", mnemonic,RT,RD,SEL);
62 } else {
63
64 // just print the first dest... if there's a second one,
65 // it's generally implicit
66 if (_numDestRegs > 0) {
67 printReg(ss, _destRegIdx[0]);
68 }
69
70 ss << ", ";
71
72 // just print the first two source regs... if there's
73 // a third one, it's a read-modify-write dest (Rc),
74 // e.g. for CMOVxx
75 if (_numSrcRegs > 0) {
76 printReg(ss, _srcRegIdx[0]);
77 }
78
79 if (_numSrcRegs > 1) {
80 ss << ", ";
81 printReg(ss, _srcRegIdx[1]);
82 }
83 }
84
85 return ss.str();
86 }
87
88 std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
89 {
90 std::stringstream ss;
91 ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
92 return ss.str();
93 }
94
95 std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
96 {
97 std::stringstream ss;
98 ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
99 return ss.str();
100 }
101
102}};
103
104def format System(code, *flags) {{
105 iop = InstObjParams(name, Name, 'Control', CodeBlock(code), flags)
106 header_output = BasicDeclare.subst(iop)
107 decoder_output = BasicConstructor.subst(iop)
108 decode_block = BasicDecode.subst(iop)
109 exec_output = BasicExecute.subst(iop)
110}};
111
112def format CP0Control(code, *flags) {{
113 iop = InstObjParams(name, Name, 'CP0Control', CodeBlock(code), flags)
114 header_output = BasicDeclare.subst(iop)
115 decoder_output = BasicConstructor.subst(iop)
116 decode_block = BasicDecode.subst(iop)
117 exec_output = BasicExecute.subst(iop)
118}};
119
120def format CP1Control(code, *flags) {{
121 iop = InstObjParams(name, Name, 'CP1Control', CodeBlock(code), flags)
122 header_output = BasicDeclare.subst(iop)
123 decoder_output = BasicConstructor.subst(iop)
124 decode_block = BasicDecode.subst(iop)
125 exec_output = BasicExecute.subst(iop)
126}};
127
128
31////////////////////////////////////////////////////////////////////
32//
33// Integer operate instructions
34//
35
36//Outputs to decoder.hh
37output header {{
38
39 class Control : public MipsStaticInst
40 {
41 protected:
42
43 /// Constructor
44 Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
45 MipsStaticInst(mnem, _machInst, __opClass)
46 {
47 }
48
49 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
50 };
51
52 class CP0Control : public Control
53 {
54 protected:
55
56 /// Constructor
57 CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
58 Control(mnem, _machInst, __opClass)
59 {
60 }
61
62 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
63 };
64
65 class CP1Control : public Control
66 {
67 protected:
68
69 /// Constructor
70 CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
71 Control(mnem, _machInst, __opClass)
72 {
73 }
74
75 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
76 };
77
78}};
79
80//Outputs to decoder.cc
81output decoder {{
82 std::string Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
83 {
84 std::stringstream ss;
85
86 ccprintf(ss, "%-10s ", mnemonic);
87
88 if (mnemonic == "mfc0" || mnemonic == "mtc0") {
89 ccprintf(ss, "%-10s %d,%d,%d", mnemonic,RT,RD,SEL);
90 } else {
91
92 // just print the first dest... if there's a second one,
93 // it's generally implicit
94 if (_numDestRegs > 0) {
95 printReg(ss, _destRegIdx[0]);
96 }
97
98 ss << ", ";
99
100 // just print the first two source regs... if there's
101 // a third one, it's a read-modify-write dest (Rc),
102 // e.g. for CMOVxx
103 if (_numSrcRegs > 0) {
104 printReg(ss, _srcRegIdx[0]);
105 }
106
107 if (_numSrcRegs > 1) {
108 ss << ", ";
109 printReg(ss, _srcRegIdx[1]);
110 }
111 }
112
113 return ss.str();
114 }
115
116 std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
117 {
118 std::stringstream ss;
119 ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
120 return ss.str();
121 }
122
123 std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
124 {
125 std::stringstream ss;
126 ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
127 return ss.str();
128 }
129
130}};
131
132def format System(code, *flags) {{
133 iop = InstObjParams(name, Name, 'Control', CodeBlock(code), flags)
134 header_output = BasicDeclare.subst(iop)
135 decoder_output = BasicConstructor.subst(iop)
136 decode_block = BasicDecode.subst(iop)
137 exec_output = BasicExecute.subst(iop)
138}};
139
140def format CP0Control(code, *flags) {{
141 iop = InstObjParams(name, Name, 'CP0Control', CodeBlock(code), flags)
142 header_output = BasicDeclare.subst(iop)
143 decoder_output = BasicConstructor.subst(iop)
144 decode_block = BasicDecode.subst(iop)
145 exec_output = BasicExecute.subst(iop)
146}};
147
148def format CP1Control(code, *flags) {{
149 iop = InstObjParams(name, Name, 'CP1Control', CodeBlock(code), flags)
150 header_output = BasicDeclare.subst(iop)
151 decoder_output = BasicConstructor.subst(iop)
152 decode_block = BasicDecode.subst(iop)
153 exec_output = BasicExecute.subst(iop)
154}};
155
156