branch.isa (5269:0bdd8bbdc79f) branch.isa (7720:65d338a8dba4)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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84 disp(OFFSET << 2)
85 {
86 //If Bit 17 is 1 then Sign Extend
87 if ( (disp & 0x00020000) > 0 ) {
88 disp |= 0xFFFE0000;
89 }
90 }
91
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 75 unchanged lines hidden (view full) ---

84 disp(OFFSET << 2)
85 {
86 //If Bit 17 is 1 then Sign Extend
87 if ( (disp & 0x00020000) > 0 ) {
88 disp |= 0xFFFE0000;
89 }
90 }
91
92 Addr branchTarget(Addr branchPC) const;
92 MipsISA::PCState branchTarget(const MipsISA::PCState &branchPC) const;
93
94 std::string
95 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
96 };
97
98 /**
99 * Base class for jumps (register-indirect control transfers). In
100 * the Mips ISA, these are always unconditional.

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111 public:
112 /// Constructor
113 Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
114 : PCDependentDisassembly(mnem, _machInst, __opClass),
115 disp(JMPTARG << 2)
116 {
117 }
118
93
94 std::string
95 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
96 };
97
98 /**
99 * Base class for jumps (register-indirect control transfers). In
100 * the Mips ISA, these are always unconditional.

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111 public:
112 /// Constructor
113 Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
114 : PCDependentDisassembly(mnem, _machInst, __opClass),
115 disp(JMPTARG << 2)
116 {
117 }
118
119 Addr branchTarget(ThreadContext *tc) const;
119 MipsISA::PCState branchTarget(ThreadContext *tc) const;
120
121 std::string
122 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
123 };
124}};
125
126output decoder {{
120
121 std::string
122 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
123 };
124}};
125
126output decoder {{
127 Addr
128 Branch::branchTarget(Addr branchPC) const
127 MipsISA::PCState
128 Branch::branchTarget(const MipsISA::PCState &branchPC) const
129 {
129 {
130 return branchPC + 4 + disp;
130 MipsISA::PCState target = branchPC;
131 target.advance();
132 target.npc(branchPC.pc() + sizeof(MachInst) + disp);
133 target.nnpc(target.npc() + sizeof(MachInst));
134 return target;
131 }
132
135 }
136
133 Addr
137 MipsISA::PCState
134 Jump::branchTarget(ThreadContext *tc) const
135 {
138 Jump::branchTarget(ThreadContext *tc) const
139 {
136 Addr NPC = tc->readNextPC();
137 return (NPC & 0xF0000000) | (disp);
140 MipsISA::PCState target = tc->pcState();
141 Addr pc = target.pc();
142 target.advance();
143 target.npc((pc & 0xF0000000) | disp);
144 target.nnpc(target.npc() + sizeof(MachInst));
145 return target;
138 }
139
140 const std::string &
141 PCDependentDisassembly::disassemble(Addr pc,
142 const SymbolTable *symtab) const
143 {
144 if (!cachedDisassembly ||
145 pc != cachedPC || symtab != cachedSymtab)

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212 printReg(ss, _srcRegIdx[1]);
213 }
214
215 return ss.str();
216 }
217}};
218
219def format Branch(code, *opt_flags) {{
146 }
147
148 const std::string &
149 PCDependentDisassembly::disassemble(Addr pc,
150 const SymbolTable *symtab) const
151 {
152 if (!cachedDisassembly ||
153 pc != cachedPC || symtab != cachedSymtab)

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220 printReg(ss, _srcRegIdx[1]);
221 }
222
223 return ss.str();
224 }
225}};
226
227def format Branch(code, *opt_flags) {{
220 not_taken_code = ' NNPC = NNPC;\n'
221 not_taken_code += '} \n'
228 not_taken_code = ''
222
223 #Build Instruction Flags
224 #Use Link & Likely Flags to Add Link/Condition Code
225 inst_flags = ('IsDirectControl', )
226 for x in opt_flags:
227 if x == 'Link':
229
230 #Build Instruction Flags
231 #Use Link & Likely Flags to Add Link/Condition Code
232 inst_flags = ('IsDirectControl', )
233 for x in opt_flags:
234 if x == 'Link':
228 code += 'R31 = NNPC;\n'
235 code += 'R31 = pc.nnpc();\n'
229 elif x == 'Likely':
236 elif x == 'Likely':
230 not_taken_code = ' NPC = NNPC;\n'
231 not_taken_code += ' NNPC = NNPC + 4;\n'
232 not_taken_code += '} \n'
237 not_taken_code = 'pc.advance();'
233 inst_flags += ('IsCondDelaySlot', )
234 else:
235 inst_flags += (x, )
236
237 #Take into account uncond. branch instruction
238 if 'cond = 1' in code:
239 inst_flags += ('IsUncondControl', )
240 else:
241 inst_flags += ('IsCondControl', )
242
243 #Condition code
238 inst_flags += ('IsCondDelaySlot', )
239 else:
240 inst_flags += (x, )
241
242 #Take into account uncond. branch instruction
243 if 'cond = 1' in code:
244 inst_flags += ('IsUncondControl', )
245 else:
246 inst_flags += ('IsCondControl', )
247
248 #Condition code
244 code = 'bool cond;\n' + code
245 code += 'if (cond) {\n'
246 code += ' NNPC = NPC + disp;\n'
247 code += '} else {\n'
248 code += not_taken_code
249 code = '''
250 bool cond;
251 MipsISA::PCState pc = PCS;
252 %(code)s
253 if (cond) {
254 pc.nnpc(pc.npc() + disp);
255 } else {
256 %(not_taken_code)s
257 }
258 PCS = pc;
259 ''' % { "code" : code, "not_taken_code" : not_taken_code }
249
250 iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
251 header_output = BasicDeclare.subst(iop)
252 decoder_output = BasicConstructor.subst(iop)
253 decode_block = BasicDecode.subst(iop)
254 exec_output = BasicExecute.subst(iop)
255}};
256
257def format DspBranch(code, *opt_flags) {{
260
261 iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
262 header_output = BasicDeclare.subst(iop)
263 decoder_output = BasicConstructor.subst(iop)
264 decode_block = BasicDecode.subst(iop)
265 exec_output = BasicExecute.subst(iop)
266}};
267
268def format DspBranch(code, *opt_flags) {{
258 not_taken_code = ' NNPC = NNPC;\n'
259 not_taken_code += '} \n'
269 not_taken_code = ''
260
261 #Build Instruction Flags
262 #Use Link & Likely Flags to Add Link/Condition Code
263 inst_flags = ('IsDirectControl', )
264 for x in opt_flags:
265 if x == 'Link':
270
271 #Build Instruction Flags
272 #Use Link & Likely Flags to Add Link/Condition Code
273 inst_flags = ('IsDirectControl', )
274 for x in opt_flags:
275 if x == 'Link':
266 code += 'R31 = NNPC;\n'
276 code += 'R32 = pc.nnpc();'
267 elif x == 'Likely':
277 elif x == 'Likely':
268 not_taken_code = ' NPC = NNPC;\n'
269 not_taken_code += ' NNPC = NNPC + 4;\n'
270 not_taken_code += '} \n'
278 not_taken_code = 'pc.advance();'
271 inst_flags += ('IsCondDelaySlot', )
272 else:
273 inst_flags += (x, )
274
275 #Take into account uncond. branch instruction
276 if 'cond = 1' in code:
277 inst_flags += ('IsUncondControl', )
278 else:
279 inst_flags += ('IsCondControl', )
280
279 inst_flags += ('IsCondDelaySlot', )
280 else:
281 inst_flags += (x, )
282
283 #Take into account uncond. branch instruction
284 if 'cond = 1' in code:
285 inst_flags += ('IsUncondControl', )
286 else:
287 inst_flags += ('IsCondControl', )
288
281 #Declaration code
282 decl_code = 'bool cond;\n'
283 decl_code += 'uint32_t dspctl;\n'
284
285 #Fetch code
286 fetch_code = 'dspctl = DSPControl;\n'
287
288 #Condition code
289 #Condition code
289 code = decl_code + fetch_code + code
290 code += 'if (cond) {\n'
291 code += ' NNPC = NPC + disp;\n'
292 code += '} else {\n'
293 code += not_taken_code
290 code = '''
291 MipsISA::PCState pc = PCS;
292 bool cond;
293 uint32_t dspctl = DSPControl;
294 %(code)s
295 if (cond) {
296 pc.nnpc(pc.npc() + disp);
297 } else {
298 %(not_taken_code)s
299 }
300 PCS = pc;
301 ''' % { "code" : code, "not_taken_code" : not_taken_code }
294
295 iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
296 header_output = BasicDeclare.subst(iop)
297 decoder_output = BasicConstructor.subst(iop)
298 decode_block = BasicDecode.subst(iop)
299 exec_output = BasicExecute.subst(iop)
300}};
301
302def format Jump(code, *opt_flags) {{
303 #Build Instruction Flags
304 #Use Link Flag to Add Link Code
305 inst_flags = ('IsIndirectControl', 'IsUncondControl')
306 for x in opt_flags:
307 if x == 'Link':
302
303 iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
304 header_output = BasicDeclare.subst(iop)
305 decoder_output = BasicConstructor.subst(iop)
306 decode_block = BasicDecode.subst(iop)
307 exec_output = BasicExecute.subst(iop)
308}};
309
310def format Jump(code, *opt_flags) {{
311 #Build Instruction Flags
312 #Use Link Flag to Add Link Code
313 inst_flags = ('IsIndirectControl', 'IsUncondControl')
314 for x in opt_flags:
315 if x == 'Link':
308 code = 'R31 = NNPC;\n' + code
316 code = '''
317 R31 = pc.nnpc();
318 ''' + code
309 elif x == 'ClearHazards':
310 code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
311 else:
312 inst_flags += (x, )
313
319 elif x == 'ClearHazards':
320 code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
321 else:
322 inst_flags += (x, )
323
324 code = '''
325 MipsISA::PCState pc = PCS;
326 ''' + code
327
314 iop = InstObjParams(name, Name, 'Jump', code, inst_flags)
315 header_output = BasicDeclare.subst(iop)
316 decoder_output = BasicConstructor.subst(iop)
317 decode_block = BasicDecode.subst(iop)
318 exec_output = BasicExecute.subst(iop)
319}};
320
321
322
323
328 iop = InstObjParams(name, Name, 'Jump', code, inst_flags)
329 header_output = BasicDeclare.subst(iop)
330 decoder_output = BasicConstructor.subst(iop)
331 decode_block = BasicDecode.subst(iop)
332 exec_output = BasicExecute.subst(iop)
333}};
334
335
336
337