branch.isa (3951:727778d649ae) branch.isa (4661:44458219add1)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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31////////////////////////////////////////////////////////////////////
32//
33// Control transfer instructions
34//
35
36output header {{
37
38#include <iostream>
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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31////////////////////////////////////////////////////////////////////
32//
33// Control transfer instructions
34//
35
36output header {{
37
38#include <iostream>
39 using namespace std;
39
40 /**
41 * Base class for instructions whose disassembly is not purely a
42 * function of the machine instruction (i.e., it depends on the
43 * PC). This class overrides the disassemble() method to check
44 * the PC and symbol table values before re-using a cached
45 * disassembly string. This is necessary for branches and jumps,
46 * where the disassembly string includes the target address (which

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211 ss << ", ";
212 printReg(ss, _srcRegIdx[1]);
213 }
214
215 return ss.str();
216 }
217}};
218
40
41 /**
42 * Base class for instructions whose disassembly is not purely a
43 * function of the machine instruction (i.e., it depends on the
44 * PC). This class overrides the disassemble() method to check
45 * the PC and symbol table values before re-using a cached
46 * disassembly string. This is necessary for branches and jumps,
47 * where the disassembly string includes the target address (which

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212 ss << ", ";
213 printReg(ss, _srcRegIdx[1]);
214 }
215
216 return ss.str();
217 }
218}};
219
219def format Branch(code,*opt_flags) {{
220def format Branch(code, *opt_flags) {{
220 not_taken_code = ' NNPC = NNPC;\n'
221 not_taken_code += '} \n'
222
223 #Build Instruction Flags
224 #Use Link & Likely Flags to Add Link/Condition Code
225 inst_flags = ('IsDirectControl', )
226 for x in opt_flags:
227 if x == 'Link':
228 code += 'R31 = NNPC;\n'
229 elif x == 'Likely':
230 not_taken_code = ' NPC = NNPC;\n'
231 not_taken_code += ' NNPC = NNPC + 4;\n'
232 not_taken_code += '} \n'
221 not_taken_code = ' NNPC = NNPC;\n'
222 not_taken_code += '} \n'
223
224 #Build Instruction Flags
225 #Use Link & Likely Flags to Add Link/Condition Code
226 inst_flags = ('IsDirectControl', )
227 for x in opt_flags:
228 if x == 'Link':
229 code += 'R31 = NNPC;\n'
230 elif x == 'Likely':
231 not_taken_code = ' NPC = NNPC;\n'
232 not_taken_code += ' NNPC = NNPC + 4;\n'
233 not_taken_code += '} \n'
233 inst_flags = ('IsCondDelaySlot', )
234 inst_flags += ('IsCondDelaySlot', )
234 else:
235 inst_flags += (x, )
236
237 #Take into account uncond. branch instruction
235 else:
236 inst_flags += (x, )
237
238 #Take into account uncond. branch instruction
238 if 'cond == 1' in code:
239 inst_flags += ('IsUnCondControl', )
239 if 'cond = 1' in code:
240 inst_flags += ('IsUncondControl', )
240 else:
241 inst_flags += ('IsCondControl', )
242
243 #Condition code
244 code = 'bool cond;\n' + code
245 code += 'if (cond) {\n'
246 code += ' NNPC = NPC + disp;\n'
247 code += '} else {\n'
248 code += not_taken_code
249
250 iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
251 header_output = BasicDeclare.subst(iop)
252 decoder_output = BasicConstructor.subst(iop)
253 decode_block = BasicDecode.subst(iop)
254 exec_output = BasicExecute.subst(iop)
255}};
256
241 else:
242 inst_flags += ('IsCondControl', )
243
244 #Condition code
245 code = 'bool cond;\n' + code
246 code += 'if (cond) {\n'
247 code += ' NNPC = NPC + disp;\n'
248 code += '} else {\n'
249 code += not_taken_code
250
251 iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
252 header_output = BasicDeclare.subst(iop)
253 decoder_output = BasicConstructor.subst(iop)
254 decode_block = BasicDecode.subst(iop)
255 exec_output = BasicExecute.subst(iop)
256}};
257
258def format DspBranch(code, *opt_flags) {{
259 not_taken_code = ' NNPC = NNPC;\n'
260 not_taken_code += '} \n'
261
262 #Build Instruction Flags
263 #Use Link & Likely Flags to Add Link/Condition Code
264 inst_flags = ('IsDirectControl', )
265 for x in opt_flags:
266 if x == 'Link':
267 code += 'R31 = NNPC;\n'
268 elif x == 'Likely':
269 not_taken_code = ' NPC = NNPC;\n'
270 not_taken_code += ' NNPC = NNPC + 4;\n'
271 not_taken_code += '} \n'
272 inst_flags += ('IsCondDelaySlot', )
273 else:
274 inst_flags += (x, )
275
276 #Take into account uncond. branch instruction
277 if 'cond = 1' in code:
278 inst_flags += ('IsUncondControl', )
279 else:
280 inst_flags += ('IsCondControl', )
281
282 #Declaration code
283 decl_code = 'bool cond;\n'
284 decl_code += 'uint32_t dspctl;\n'
285
286 #Fetch code
287 fetch_code = 'dspctl = DSPControl;\n'
288
289 #Condition code
290 code = decl_code + fetch_code + code
291 code += 'if (cond) {\n'
292 code += ' NNPC = NPC + disp;\n'
293 code += '} else {\n'
294 code += not_taken_code
295
296 iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
297 header_output = BasicDeclare.subst(iop)
298 decoder_output = BasicConstructor.subst(iop)
299 decode_block = BasicDecode.subst(iop)
300 exec_output = BasicExecute.subst(iop)
301}};
302
257def format Jump(code, *opt_flags) {{
258 #Build Instruction Flags
259 #Use Link Flag to Add Link Code
260 inst_flags = ('IsIndirectControl', 'IsUncondControl')
261 for x in opt_flags:
262 if x == 'Link':
263 code = 'R31 = NNPC;\n' + code
264 elif x == 'ClearHazards':

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303def format Jump(code, *opt_flags) {{
304 #Build Instruction Flags
305 #Use Link Flag to Add Link Code
306 inst_flags = ('IsIndirectControl', 'IsUncondControl')
307 for x in opt_flags:
308 if x == 'Link':
309 code = 'R31 = NNPC;\n' + code
310 elif x == 'ClearHazards':

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