branch.isa (2701:38218635db4c) | branch.isa (2706:d88c27f75121) |
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1// -*- mode:c++ -*- 2 | 1// -*- mode:c++ -*- 2 |
3// Copyright (c) 2003-2006 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell 30 |
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3//////////////////////////////////////////////////////////////////// 4// 5// Control transfer instructions 6// 7 8output header {{ 9 10#include <iostream> --- 52 unchanged lines hidden (view full) --- 63 64 Addr branchTarget(Addr branchPC) const; 65 66 std::string 67 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 68 }; 69 70 /** | 31//////////////////////////////////////////////////////////////////// 32// 33// Control transfer instructions 34// 35 36output header {{ 37 38#include <iostream> --- 52 unchanged lines hidden (view full) --- 91 92 Addr branchTarget(Addr branchPC) const; 93 94 std::string 95 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 96 }; 97 98 /** |
71 * Base class for branch likely branches (PC-relative control transfers), 72 */ 73 class BranchLikely : public PCDependentDisassembly 74 { 75 protected: 76 /// target address (signed) Displacement . 77 int32_t disp; 78 79 /// Constructor. 80 BranchLikely(const char *mnem, MachInst _machInst, OpClass __opClass) 81 : PCDependentDisassembly(mnem, _machInst, __opClass), 82 disp(OFFSET << 2) 83 { 84 85 } 86 87 Addr branchTarget(Addr branchPC) const; 88 89 std::string 90 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 91 }; 92 93 /** | |
94 * Base class for jumps (register-indirect control transfers). In 95 * the Mips ISA, these are always unconditional. 96 */ 97 class Jump : public PCDependentDisassembly 98 { 99 protected: 100 101 /// Displacement to target address (signed). --- 19 unchanged lines hidden (view full) --- 121output decoder {{ 122 Addr 123 Branch::branchTarget(Addr branchPC) const 124 { 125 return branchPC + 4 + disp; 126 } 127 128 Addr | 99 * Base class for jumps (register-indirect control transfers). In 100 * the Mips ISA, these are always unconditional. 101 */ 102 class Jump : public PCDependentDisassembly 103 { 104 protected: 105 106 /// Displacement to target address (signed). --- 19 unchanged lines hidden (view full) --- 126output decoder {{ 127 Addr 128 Branch::branchTarget(Addr branchPC) const 129 { 130 return branchPC + 4 + disp; 131 } 132 133 Addr |
129 BranchLikely::branchTarget(Addr branchPC) const 130 { 131 return branchPC + 4 + disp; 132 } 133 134 Addr | |
135 Jump::branchTarget(ThreadContext *tc) const 136 { 137 Addr NPC = tc->readPC() + 4; 138 uint64_t Rb = tc->readIntReg(_srcRegIdx[0]); 139 return (Rb & ~3) | (NPC & 1); 140 } 141 142 const std::string & --- 23 unchanged lines hidden (view full) --- 166 ccprintf(ss, "%-10s ", mnemonic); 167 168 // There's only one register arg (RA), but it could be 169 // either a source (the condition for conditional 170 // branches) or a destination (the link reg for 171 // unconditional branches) 172 if (_numSrcRegs == 1) { 173 printReg(ss, _srcRegIdx[0]); | 134 Jump::branchTarget(ThreadContext *tc) const 135 { 136 Addr NPC = tc->readPC() + 4; 137 uint64_t Rb = tc->readIntReg(_srcRegIdx[0]); 138 return (Rb & ~3) | (NPC & 1); 139 } 140 141 const std::string & --- 23 unchanged lines hidden (view full) --- 165 ccprintf(ss, "%-10s ", mnemonic); 166 167 // There's only one register arg (RA), but it could be 168 // either a source (the condition for conditional 169 // branches) or a destination (the link reg for 170 // unconditional branches) 171 if (_numSrcRegs == 1) { 172 printReg(ss, _srcRegIdx[0]); |
174 ss << ","; | 173 ss << ", "; |
175 } else if(_numSrcRegs == 2) { 176 printReg(ss, _srcRegIdx[0]); | 174 } else if(_numSrcRegs == 2) { 175 printReg(ss, _srcRegIdx[0]); |
177 ss << ","; | 176 ss << ", "; |
178 printReg(ss, _srcRegIdx[1]); | 177 printReg(ss, _srcRegIdx[1]); |
179 ss << ","; | 178 ss << ", "; |
180 } 181 182 Addr target = pc + 4 + disp; 183 184 std::string str; 185 if (symtab && symtab->findSymbol(target, str)) 186 ss << str; 187 else 188 ccprintf(ss, "0x%x", target); 189 | 179 } 180 181 Addr target = pc + 4 + disp; 182 183 std::string str; 184 if (symtab && symtab->findSymbol(target, str)) 185 ss << str; 186 else 187 ccprintf(ss, "0x%x", target); 188 |
190 string inst_name = mnemonic; 191 192 if (inst_name.substr(inst_name.length()-2,inst_name.length()) == "al"){ 193 ccprintf(ss, " (r31=0x%x)",pc+8); 194 } 195 | |
196 return ss.str(); 197 } 198 199 std::string | 189 return ss.str(); 190 } 191 192 std::string |
200 BranchLikely::generateDisassembly(Addr pc, const SymbolTable *symtab) const 201 { 202 std::stringstream ss; 203 204 ccprintf(ss, "%-10s ", mnemonic); 205 206 // There's only one register arg (RA), but it could be 207 // either a source (the condition for conditional 208 // branches) or a destination (the link reg for 209 // unconditional branches) 210 if (_numSrcRegs > 0) { 211 printReg(ss, _srcRegIdx[0]); 212 ss << ","; 213 } 214 else if (_numDestRegs > 0) { 215 printReg(ss, _destRegIdx[0]); 216 ss << ","; 217 } 218 219 Addr target = pc + 4 + disp; 220 221 std::string str; 222 if (symtab && symtab->findSymbol(target, str)) 223 ss << str; 224 else 225 ccprintf(ss, "0x%x", target); 226 227 return ss.str(); 228 } 229 230 std::string | |
231 Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const 232 { 233 std::stringstream ss; 234 235 ccprintf(ss, "%-10s ", mnemonic); 236 237 if ( mnemonic == "jal" ) { 238 Addr npc = pc + 4; 239 ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp); 240 } else if (_numSrcRegs == 0) { 241 std::string str; 242 if (symtab && symtab->findSymbol(disp, str)) 243 ss << str; 244 else 245 ccprintf(ss, "0x%x", disp); 246 } else if (_numSrcRegs == 1) { 247 printReg(ss, _srcRegIdx[0]); 248 } else if(_numSrcRegs == 2) { 249 printReg(ss, _srcRegIdx[0]); | 193 Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const 194 { 195 std::stringstream ss; 196 197 ccprintf(ss, "%-10s ", mnemonic); 198 199 if ( mnemonic == "jal" ) { 200 Addr npc = pc + 4; 201 ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp); 202 } else if (_numSrcRegs == 0) { 203 std::string str; 204 if (symtab && symtab->findSymbol(disp, str)) 205 ss << str; 206 else 207 ccprintf(ss, "0x%x", disp); 208 } else if (_numSrcRegs == 1) { 209 printReg(ss, _srcRegIdx[0]); 210 } else if(_numSrcRegs == 2) { 211 printReg(ss, _srcRegIdx[0]); |
250 ss << ","; | 212 ss << ", "; |
251 printReg(ss, _srcRegIdx[1]); | 213 printReg(ss, _srcRegIdx[1]); |
252 } else { 253 panic(">= 3 Source Registers!!!"); | |
254 } 255 256 return ss.str(); 257 } 258}}; 259 | 214 } 215 216 return ss.str(); 217 } 218}}; 219 |
260def format Branch(code,*flags) {{ 261 #Add Link Code if Link instruction 262 strlen = len(name) 263 if name[strlen-2:] == 'al': 264 code += 'R31 = NNPC;\n' | 220def format Branch(code,*opt_flags) {{ 221 not_taken_code = ' NNPC = NNPC;\n' 222 not_taken_code += '} \n' |
265 | 223 |
224 #Build Instruction Flags 225 #Use Link & Likely Flags to Add Link/Condition Code 226 inst_flags = ('IsDirectControl', ) 227 for x in opt_flags: 228 if x == 'Link': 229 code += 'R31 = NNPC;\n' 230 elif x == 'Likely': 231 not_taken_code = ' NPC = NNPC;\n' 232 not_taken_code += ' NNPC = NNPC + 4;\n' 233 not_taken_code += '} \n' 234 inst_flags = ('IsCondDelaySlot', ) 235 else: 236 inst_flags += (x, ) 237 238 if 'cond == 1' in code: 239 inst_flags += ('IsCondControl', ) 240 else: 241 inst_flags += ('IsUncondControl', ) 242 |
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266 #Condition code 267 code = 'bool cond;\n' + code 268 code += 'if (cond) {\n' 269 code += ' NNPC = NPC + disp;\n' 270 code += '} else {\n' | 243 #Condition code 244 code = 'bool cond;\n' + code 245 code += 'if (cond) {\n' 246 code += ' NNPC = NPC + disp;\n' 247 code += '} else {\n' |
271 code += ' NNPC = NNPC;\n' 272 code += '} \n' | 248 code += not_taken_code |
273 | 249 |
274 iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), 275 ('IsDirectControl', 'IsCondControl')) 276 | 250 iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), inst_flags) |
277 header_output = BasicDeclare.subst(iop) 278 decoder_output = BasicConstructor.subst(iop) 279 decode_block = BasicDecode.subst(iop) 280 exec_output = BasicExecute.subst(iop) 281}}; 282 | 251 header_output = BasicDeclare.subst(iop) 252 decoder_output = BasicConstructor.subst(iop) 253 decode_block = BasicDecode.subst(iop) 254 exec_output = BasicExecute.subst(iop) 255}}; 256 |
283 284def format BranchLikely(code,*flags) {{ 285 #Add Link Code if Link instruction 286 strlen = len(name) 287 if name[strlen-3:] == 'all': 288 code += 'R31 = NNPC;\n' 289 290 #Condition code 291 code = 'bool cond;\n' + code 292 code += 'if (cond) {' 293 code += 'NNPC = NPC + disp;\n' 294 code += '} \n' 295 296 297 iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), 298 ('IsDirectControl', 'IsCondControl','IsCondDelaySlot')) 299 300 header_output = BasicDeclare.subst(iop) 301 decoder_output = BasicConstructor.subst(iop) 302 decode_block = BasicDecode.subst(iop) 303 exec_output = BasicExecute.subst(iop) 304}}; 305 306def format Jump(code,*flags) {{ 307 #Add Link Code if Link instruction 308 strlen = len(name) 309 if strlen > 1 and name[1:] == 'al': | 257def format Jump(code, *opt_flags) {{ 258 #Build Instruction Flags 259 #Use Link Flag to Add Link Code 260 inst_flags = ('IsIndirectControl', 'IsUncondControl') 261 for x in opt_flags: 262 if x == 'Link': |
310 code = 'R31 = NNPC;\n' + code | 263 code = 'R31 = NNPC;\n' + code |
264 elif x == 'ClearHazards': 265 code += '/* Code Needed to Clear Execute & Inst Hazards */\n' 266 else: 267 inst_flags += (x, ) |
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311 | 268 |
312 313 iop = InstObjParams(name, Name, 'Jump', CodeBlock(code),\ 314 ('IsIndirectControl', 'IsUncondControl')) 315 | 269 iop = InstObjParams(name, Name, 'Jump', CodeBlock(code), inst_flags) |
316 header_output = BasicDeclare.subst(iop) 317 decoder_output = BasicConstructor.subst(iop) 318 decode_block = BasicDecode.subst(iop) 319 exec_output = BasicExecute.subst(iop) 320}}; 321 322 323 324 | 270 header_output = BasicDeclare.subst(iop) 271 decoder_output = BasicConstructor.subst(iop) 272 decode_block = BasicDecode.subst(iop) 273 exec_output = BasicExecute.subst(iop) 274}}; 275 276 277 278 |