branch.isa (2632:1bb2f91485ea) branch.isa (2686:f0d591379ac3)
1// -*- mode:c++ -*-
2
3////////////////////////////////////////////////////////////////////
4//
5// Control transfer instructions
6//
7
8output header {{

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63
64 Addr branchTarget(Addr branchPC) const;
65
66 std::string
67 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
68 };
69
70 /**
1// -*- mode:c++ -*-
2
3////////////////////////////////////////////////////////////////////
4//
5// Control transfer instructions
6//
7
8output header {{

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63
64 Addr branchTarget(Addr branchPC) const;
65
66 std::string
67 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
68 };
69
70 /**
71 * Base class for branch likely branches (PC-relative control transfers),
72 */
73 class BranchLikely : public PCDependentDisassembly
74 {
75 protected:
76 /// target address (signed) Displacement .
77 int32_t disp;
78
79 /// Constructor.
80 BranchLikely(const char *mnem, MachInst _machInst, OpClass __opClass)
81 : PCDependentDisassembly(mnem, _machInst, __opClass),
82 disp(OFFSET << 2)
83 {
84
85 }
86
87 Addr branchTarget(Addr branchPC) const;
88
89 std::string
90 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
91 };
92
93 /**
94 * Base class for jumps (register-indirect control transfers). In
95 * the Mips ISA, these are always unconditional.
96 */
97 class Jump : public PCDependentDisassembly
98 {
99 protected:
100
101 /// Displacement to target address (signed).

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121output decoder {{
122 Addr
123 Branch::branchTarget(Addr branchPC) const
124 {
125 return branchPC + 4 + disp;
126 }
127
128 Addr
71 * Base class for jumps (register-indirect control transfers). In
72 * the Mips ISA, these are always unconditional.
73 */
74 class Jump : public PCDependentDisassembly
75 {
76 protected:
77
78 /// Displacement to target address (signed).

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98output decoder {{
99 Addr
100 Branch::branchTarget(Addr branchPC) const
101 {
102 return branchPC + 4 + disp;
103 }
104
105 Addr
129 BranchLikely::branchTarget(Addr branchPC) const
130 {
131 return branchPC + 4 + disp;
132 }
133
134 Addr
135 Jump::branchTarget(ExecContext *xc) const
136 {
137 Addr NPC = xc->readPC() + 4;
138 uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
139 return (Rb & ~3) | (NPC & 1);
140 }
141
142 const std::string &

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166 ccprintf(ss, "%-10s ", mnemonic);
167
168 // There's only one register arg (RA), but it could be
169 // either a source (the condition for conditional
170 // branches) or a destination (the link reg for
171 // unconditional branches)
172 if (_numSrcRegs == 1) {
173 printReg(ss, _srcRegIdx[0]);
106 Jump::branchTarget(ExecContext *xc) const
107 {
108 Addr NPC = xc->readPC() + 4;
109 uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
110 return (Rb & ~3) | (NPC & 1);
111 }
112
113 const std::string &

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137 ccprintf(ss, "%-10s ", mnemonic);
138
139 // There's only one register arg (RA), but it could be
140 // either a source (the condition for conditional
141 // branches) or a destination (the link reg for
142 // unconditional branches)
143 if (_numSrcRegs == 1) {
144 printReg(ss, _srcRegIdx[0]);
174 ss << ",";
145 ss << ", ";
175 } else if(_numSrcRegs == 2) {
176 printReg(ss, _srcRegIdx[0]);
146 } else if(_numSrcRegs == 2) {
147 printReg(ss, _srcRegIdx[0]);
177 ss << ",";
148 ss << ", ";
178 printReg(ss, _srcRegIdx[1]);
149 printReg(ss, _srcRegIdx[1]);
179 ss << ",";
150 ss << ", ";
180 }
181
182 Addr target = pc + 4 + disp;
183
184 std::string str;
185 if (symtab && symtab->findSymbol(target, str))
186 ss << str;
187 else
188 ccprintf(ss, "0x%x", target);
189
151 }
152
153 Addr target = pc + 4 + disp;
154
155 std::string str;
156 if (symtab && symtab->findSymbol(target, str))
157 ss << str;
158 else
159 ccprintf(ss, "0x%x", target);
160
190 string inst_name = mnemonic;
191
192 if (inst_name.substr(inst_name.length()-2,inst_name.length()) == "al"){
193 ccprintf(ss, " (r31=0x%x)",pc+8);
194 }
195
196 return ss.str();
197 }
198
199 std::string
161 return ss.str();
162 }
163
164 std::string
200 BranchLikely::generateDisassembly(Addr pc, const SymbolTable *symtab) const
201 {
202 std::stringstream ss;
203
204 ccprintf(ss, "%-10s ", mnemonic);
205
206 // There's only one register arg (RA), but it could be
207 // either a source (the condition for conditional
208 // branches) or a destination (the link reg for
209 // unconditional branches)
210 if (_numSrcRegs > 0) {
211 printReg(ss, _srcRegIdx[0]);
212 ss << ",";
213 }
214 else if (_numDestRegs > 0) {
215 printReg(ss, _destRegIdx[0]);
216 ss << ",";
217 }
218
219 Addr target = pc + 4 + disp;
220
221 std::string str;
222 if (symtab && symtab->findSymbol(target, str))
223 ss << str;
224 else
225 ccprintf(ss, "0x%x", target);
226
227 return ss.str();
228 }
229
230 std::string
231 Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
232 {
233 std::stringstream ss;
234
235 ccprintf(ss, "%-10s ", mnemonic);
236
237 if ( mnemonic == "jal" ) {
238 Addr npc = pc + 4;
239 ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
240 } else if (_numSrcRegs == 0) {
241 std::string str;
242 if (symtab && symtab->findSymbol(disp, str))
243 ss << str;
244 else
245 ccprintf(ss, "0x%x", disp);
246 } else if (_numSrcRegs == 1) {
247 printReg(ss, _srcRegIdx[0]);
248 } else if(_numSrcRegs == 2) {
249 printReg(ss, _srcRegIdx[0]);
165 Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
166 {
167 std::stringstream ss;
168
169 ccprintf(ss, "%-10s ", mnemonic);
170
171 if ( mnemonic == "jal" ) {
172 Addr npc = pc + 4;
173 ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
174 } else if (_numSrcRegs == 0) {
175 std::string str;
176 if (symtab && symtab->findSymbol(disp, str))
177 ss << str;
178 else
179 ccprintf(ss, "0x%x", disp);
180 } else if (_numSrcRegs == 1) {
181 printReg(ss, _srcRegIdx[0]);
182 } else if(_numSrcRegs == 2) {
183 printReg(ss, _srcRegIdx[0]);
250 ss << ",";
184 ss << ", ";
251 printReg(ss, _srcRegIdx[1]);
185 printReg(ss, _srcRegIdx[1]);
252 } else {
253 panic(">= 3 Source Registers!!!");
254 }
255
256 return ss.str();
257 }
258}};
259
186 }
187
188 return ss.str();
189 }
190}};
191
260def format Branch(code,*flags) {{
261 #Add Link Code if Link instruction
262 strlen = len(name)
263 if name[strlen-2:] == 'al':
264 code += 'R31 = NNPC;\n'
192def format Branch(code,*opt_flags) {{
193 not_taken_code = ' NNPC = NNPC;\n'
194 not_taken_code += '} \n'
265
195
196 #Build Instruction Flags
197 #Use Link & Likely Flags to Add Link/Condition Code
198 inst_flags = ('IsDirectControl', )
199 for x in opt_flags:
200 if x == 'Link':
201 code += 'R31 = NNPC;\n'
202 elif x == 'Likely':
203 not_taken_code = ' NPC = NNPC;\n'
204 not_taken_code += ' NNPC = NNPC + 4;\n'
205 not_taken_code += '} \n'
206 inst_flags = ('IsCondDelaySlot', )
207 else:
208 inst_flags += (x, )
209
210 if 'cond == 1' in code:
211 inst_flags += ('IsCondControl', )
212 else:
213 inst_flags += ('IsUncondControl', )
214
266 #Condition code
267 code = 'bool cond;\n' + code
268 code += 'if (cond) {\n'
269 code += ' NNPC = NPC + disp;\n'
270 code += '} else {\n'
215 #Condition code
216 code = 'bool cond;\n' + code
217 code += 'if (cond) {\n'
218 code += ' NNPC = NPC + disp;\n'
219 code += '} else {\n'
271 code += ' NNPC = NNPC;\n'
272 code += '} \n'
220 code += not_taken_code
273
221
274 iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
275 ('IsDirectControl', 'IsCondControl'))
276
222 iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), inst_flags)
277 header_output = BasicDeclare.subst(iop)
278 decoder_output = BasicConstructor.subst(iop)
279 decode_block = BasicDecode.subst(iop)
280 exec_output = BasicExecute.subst(iop)
281}};
282
223 header_output = BasicDeclare.subst(iop)
224 decoder_output = BasicConstructor.subst(iop)
225 decode_block = BasicDecode.subst(iop)
226 exec_output = BasicExecute.subst(iop)
227}};
228
283
284def format BranchLikely(code,*flags) {{
285 #Add Link Code if Link instruction
286 strlen = len(name)
287 if name[strlen-3:] == 'all':
288 code += 'R31 = NNPC;\n'
289
290 #Condition code
291 code = 'bool cond;\n' + code
292 code += 'if (cond) {'
293 code += 'NNPC = NPC + disp;\n'
294 code += '} \n'
295
296
297 iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
298 ('IsDirectControl', 'IsCondControl','IsCondDelaySlot'))
299
300 header_output = BasicDeclare.subst(iop)
301 decoder_output = BasicConstructor.subst(iop)
302 decode_block = BasicDecode.subst(iop)
303 exec_output = BasicExecute.subst(iop)
304}};
305
306def format Jump(code,*flags) {{
307 #Add Link Code if Link instruction
308 strlen = len(name)
309 if strlen > 1 and name[1:] == 'al':
229def format Jump(code, *opt_flags) {{
230 #Build Instruction Flags
231 #Use Link Flag to Add Link Code
232 inst_flags = ('IsIndirectControl', 'IsUncondControl')
233 for x in opt_flags:
234 if x == 'Link':
310 code = 'R31 = NNPC;\n' + code
235 code = 'R31 = NNPC;\n' + code
236 elif x == 'ClearHazards':
237 code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
238 else:
239 inst_flags += (x, )
311
240
312
313 iop = InstObjParams(name, Name, 'Jump', CodeBlock(code),\
314 ('IsIndirectControl', 'IsUncondControl'))
315
241 iop = InstObjParams(name, Name, 'Jump', CodeBlock(code), inst_flags)
316 header_output = BasicDeclare.subst(iop)
317 decoder_output = BasicConstructor.subst(iop)
318 decode_block = BasicDecode.subst(iop)
319 exec_output = BasicExecute.subst(iop)
320}};
321
322
323
324
242 header_output = BasicDeclare.subst(iop)
243 decoder_output = BasicConstructor.subst(iop)
244 decode_block = BasicDecode.subst(iop)
245 exec_output = BasicExecute.subst(iop)
246}};
247
248
249
250