1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 75 unchanged lines hidden (view full) --- 84 disp(OFFSET << 2) 85 { 86 //If Bit 17 is 1 then Sign Extend 87 if ( (disp & 0x00020000) > 0 ) { 88 disp |= 0xFFFE0000; 89 } 90 } 91 |
92 MipsISA::PCState branchTarget( 93 const MipsISA::PCState &branchPC) const override; |
94 95 /// Explicitly import the otherwise hidden branchTarget 96 using StaticInst::branchTarget; 97 |
98 std::string generateDisassembly( 99 Addr pc, const SymbolTable *symtab) const override; |
100 }; 101 102 /** 103 * Base class for jumps (register-indirect control transfers). In 104 * the Mips ISA, these are always unconditional. 105 */ 106 class Jump : public PCDependentDisassembly 107 { --- 7 unchanged lines hidden (view full) --- 115 public: 116 /// Constructor 117 Jump(const char *mnem, MachInst _machInst, OpClass __opClass) 118 : PCDependentDisassembly(mnem, _machInst, __opClass), 119 disp(JMPTARG << 2) 120 { 121 } 122 |
123 MipsISA::PCState branchTarget(ThreadContext *tc) const override; |
124 125 /// Explicitly import the otherwise hidden branchTarget 126 using StaticInst::branchTarget; 127 |
128 std::string generateDisassembly( 129 Addr pc, const SymbolTable *symtab) const override; |
130 }; 131}}; 132 133output decoder {{ 134 MipsISA::PCState 135 Branch::branchTarget(const MipsISA::PCState &branchPC) const 136 { 137 MipsISA::PCState target = branchPC; --- 199 unchanged lines hidden --- |