1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 77 unchanged lines hidden (view full) --- 86 //If Bit 17 is 1 then Sign Extend 87 if ( (disp & 0x00020000) > 0 ) { 88 disp |= 0xFFFE0000; 89 } 90 } 91 92 MipsISA::PCState branchTarget(const MipsISA::PCState &branchPC) const; 93 |
94 /// Explicitly import the otherwise hidden branchTarget 95 using StaticInst::branchTarget; 96 |
97 std::string 98 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 99 }; 100 101 /** 102 * Base class for jumps (register-indirect control transfers). In 103 * the Mips ISA, these are always unconditional. 104 */ --- 11 unchanged lines hidden (view full) --- 116 Jump(const char *mnem, MachInst _machInst, OpClass __opClass) 117 : PCDependentDisassembly(mnem, _machInst, __opClass), 118 disp(JMPTARG << 2) 119 { 120 } 121 122 MipsISA::PCState branchTarget(ThreadContext *tc) const; 123 |
124 /// Explicitly import the otherwise hidden branchTarget 125 using StaticInst::branchTarget; 126 |
127 std::string 128 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 129 }; 130}}; 131 132output decoder {{ 133 MipsISA::PCState 134 Branch::branchTarget(const MipsISA::PCState &branchPC) const --- 201 unchanged lines hidden --- |