1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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220 printReg(ss, _srcRegIdx[1]);
221 }
222
223 return ss.str();
224 }
225}};
226
227def format Branch(code, *opt_flags) {{
228 not_taken_code = ''
228 not_taken_code = 'NNPC = NNPC; NPC = NPC;'
229
230 #Build Instruction Flags
231 #Use Link & Likely Flags to Add Link/Condition Code
232 inst_flags = ('IsDirectControl', )
233 for x in opt_flags:
234 if x == 'Link':
235 code += 'R31 = pc.nnpc();\n'
235 code += 'R31 = NNPC;\n'
236 elif x == 'Likely':
237 not_taken_code = 'pc.advance();'
237 not_taken_code = 'NNPC = NPC; NPC = PC;'
238 inst_flags += ('IsCondDelaySlot', )
239 else:
240 inst_flags += (x, )
241
242 #Take into account uncond. branch instruction
243 if 'cond = 1' in code:
244 inst_flags += ('IsUncondControl', )
245 else:
246 inst_flags += ('IsCondControl', )
247
248 #Condition code
249 code = '''
250 bool cond;
251 MipsISA::PCState pc = PCS;
251 %(code)s
252 if (cond) {
254 pc.nnpc(pc.npc() + disp);
253 NNPC = NPC + disp;
254 } else {
255 %(not_taken_code)s
256 }
258 PCS = pc;
257 ''' % { "code" : code, "not_taken_code" : not_taken_code }
258
259 iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
260 header_output = BasicDeclare.subst(iop)
261 decoder_output = BasicConstructor.subst(iop)
262 decode_block = BasicDecode.subst(iop)
263 exec_output = BasicExecute.subst(iop)
264}};
265
266def format DspBranch(code, *opt_flags) {{
269 not_taken_code = ''
267 not_taken_code = 'NNPC = NNPC; NPC = NPC;'
268
269 #Build Instruction Flags
270 #Use Link & Likely Flags to Add Link/Condition Code
271 inst_flags = ('IsDirectControl', )
272 for x in opt_flags:
273 if x == 'Link':
276 code += 'R32 = pc.nnpc();'
274 code += 'R32 = NNPC;'
275 elif x == 'Likely':
278 not_taken_code = 'pc.advance();'
276 not_taken_code = 'NNPC = NPC, NPC = PC;'
277 inst_flags += ('IsCondDelaySlot', )
278 else:
279 inst_flags += (x, )
280
281 #Take into account uncond. branch instruction
282 if 'cond = 1' in code:
283 inst_flags += ('IsUncondControl', )
284 else:
285 inst_flags += ('IsCondControl', )
286
287 #Condition code
288 code = '''
291 MipsISA::PCState pc = PCS;
289 bool cond;
290 uint32_t dspctl = DSPControl;
291 %(code)s
292 if (cond) {
296 pc.nnpc(pc.npc() + disp);
293 NNPC = NPC + disp;
294 } else {
295 %(not_taken_code)s
296 }
300 PCS = pc;
297 ''' % { "code" : code, "not_taken_code" : not_taken_code }
298
299 iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
300 header_output = BasicDeclare.subst(iop)
301 decoder_output = BasicConstructor.subst(iop)
302 decode_block = BasicDecode.subst(iop)
303 exec_output = BasicExecute.subst(iop)
304}};
305
306def format Jump(code, *opt_flags) {{
307 #Build Instruction Flags
308 #Use Link Flag to Add Link Code
309 inst_flags = ('IsIndirectControl', 'IsUncondControl')
310 for x in opt_flags:
311 if x == 'Link':
312 code = '''
317 R31 = pc.nnpc();
313 R31 = NNPC;
314 ''' + code
315 elif x == 'ClearHazards':
316 code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
317 else:
318 inst_flags += (x, )
319
324 code = '''
325 MipsISA::PCState pc = PCS;
326 ''' + code
327
320 iop = InstObjParams(name, Name, 'Jump', code, inst_flags)
321 header_output = BasicDeclare.subst(iop)
322 decoder_output = BasicConstructor.subst(iop)
323 decode_block = BasicDecode.subst(iop)
324 exec_output = BasicExecute.subst(iop)
325}};
326
327
328
329