1// -*- mode:c++ -*- 2 3// Copyright (c) 2006 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 22 unchanged lines hidden (view full) --- 31//////////////////////////////////////////////////////////////////// 32// 33// Control transfer instructions 34// 35 36output header {{ 37 38#include <iostream> |
39 using namespace std; |
40 41 /** 42 * Base class for instructions whose disassembly is not purely a 43 * function of the machine instruction (i.e., it depends on the 44 * PC). This class overrides the disassemble() method to check 45 * the PC and symbol table values before re-using a cached 46 * disassembly string. This is necessary for branches and jumps, 47 * where the disassembly string includes the target address (which --- 164 unchanged lines hidden (view full) --- 212 ss << ", "; 213 printReg(ss, _srcRegIdx[1]); 214 } 215 216 return ss.str(); 217 } 218}}; 219 |
220def format Branch(code, *opt_flags) {{ |
221 not_taken_code = ' NNPC = NNPC;\n' 222 not_taken_code += '} \n' 223 224 #Build Instruction Flags 225 #Use Link & Likely Flags to Add Link/Condition Code 226 inst_flags = ('IsDirectControl', ) 227 for x in opt_flags: 228 if x == 'Link': 229 code += 'R31 = NNPC;\n' 230 elif x == 'Likely': 231 not_taken_code = ' NPC = NNPC;\n' 232 not_taken_code += ' NNPC = NNPC + 4;\n' 233 not_taken_code += '} \n' |
234 inst_flags += ('IsCondDelaySlot', ) |
235 else: 236 inst_flags += (x, ) 237 238 #Take into account uncond. branch instruction |
239 if 'cond = 1' in code: 240 inst_flags += ('IsUncondControl', ) |
241 else: 242 inst_flags += ('IsCondControl', ) 243 244 #Condition code 245 code = 'bool cond;\n' + code 246 code += 'if (cond) {\n' 247 code += ' NNPC = NPC + disp;\n' 248 code += '} else {\n' 249 code += not_taken_code 250 251 iop = InstObjParams(name, Name, 'Branch', code, inst_flags) 252 header_output = BasicDeclare.subst(iop) 253 decoder_output = BasicConstructor.subst(iop) 254 decode_block = BasicDecode.subst(iop) 255 exec_output = BasicExecute.subst(iop) 256}}; 257 |
258def format DspBranch(code, *opt_flags) {{ 259 not_taken_code = ' NNPC = NNPC;\n' 260 not_taken_code += '} \n' 261 262 #Build Instruction Flags 263 #Use Link & Likely Flags to Add Link/Condition Code 264 inst_flags = ('IsDirectControl', ) 265 for x in opt_flags: 266 if x == 'Link': 267 code += 'R31 = NNPC;\n' 268 elif x == 'Likely': 269 not_taken_code = ' NPC = NNPC;\n' 270 not_taken_code += ' NNPC = NNPC + 4;\n' 271 not_taken_code += '} \n' 272 inst_flags += ('IsCondDelaySlot', ) 273 else: 274 inst_flags += (x, ) 275 276 #Take into account uncond. branch instruction 277 if 'cond = 1' in code: 278 inst_flags += ('IsUncondControl', ) 279 else: 280 inst_flags += ('IsCondControl', ) 281 282 #Declaration code 283 decl_code = 'bool cond;\n' 284 decl_code += 'uint32_t dspctl;\n' 285 286 #Fetch code 287 fetch_code = 'dspctl = DSPControl;\n' 288 289 #Condition code 290 code = decl_code + fetch_code + code 291 code += 'if (cond) {\n' 292 code += ' NNPC = NPC + disp;\n' 293 code += '} else {\n' 294 code += not_taken_code 295 296 iop = InstObjParams(name, Name, 'Branch', code, inst_flags) 297 header_output = BasicDeclare.subst(iop) 298 decoder_output = BasicConstructor.subst(iop) 299 decode_block = BasicDecode.subst(iop) 300 exec_output = BasicExecute.subst(iop) 301}}; 302 |
303def format Jump(code, *opt_flags) {{ 304 #Build Instruction Flags 305 #Use Link Flag to Add Link Code 306 inst_flags = ('IsIndirectControl', 'IsUncondControl') 307 for x in opt_flags: 308 if x == 'Link': 309 code = 'R31 = NNPC;\n' + code 310 elif x == 'ClearHazards': --- 14 unchanged lines hidden --- |