1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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86 //If Bit 17 is 1 then Sign Extend
87 if ( (disp & 0x00020000) > 0 ) {
88 disp |= 0xFFFE0000;
89 }
90 }
91
92 MipsISA::PCState branchTarget(const MipsISA::PCState &branchPC) const;
93
94 std::string
95 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
96 };
97
98 /**
99 * Base class for jumps (register-indirect control transfers). In
100 * the Mips ISA, these are always unconditional.
101 */

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113 Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
114 : PCDependentDisassembly(mnem, _machInst, __opClass),
115 disp(JMPTARG << 2)
116 {
117 }
118
119 MipsISA::PCState branchTarget(ThreadContext *tc) const;
120
121 std::string
122 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
123 };
124}};
125
126output decoder {{
127 MipsISA::PCState
128 Branch::branchTarget(const MipsISA::PCState &branchPC) const

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