1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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84 disp(OFFSET << 2)
85 {
86 //If Bit 17 is 1 then Sign Extend
87 if ( (disp & 0x00020000) > 0 ) {
88 disp |= 0xFFFE0000;
89 }
90 }
91
92 MipsISA::PCState branchTarget(const MipsISA::PCState &branchPC) const;
93
94 std::string
95 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
96 };
97
98 /**
99 * Base class for jumps (register-indirect control transfers). In
100 * the Mips ISA, these are always unconditional.

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111 public:
112 /// Constructor
113 Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
114 : PCDependentDisassembly(mnem, _machInst, __opClass),
115 disp(JMPTARG << 2)
116 {
117 }
118
119 MipsISA::PCState branchTarget(ThreadContext *tc) const;
120
121 std::string
122 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
123 };
124}};
125
126output decoder {{
127 MipsISA::PCState
128 Branch::branchTarget(const MipsISA::PCState &branchPC) const
129 {
130 MipsISA::PCState target = branchPC;
131 target.advance();
132 target.npc(branchPC.pc() + sizeof(MachInst) + disp);
133 target.nnpc(target.npc() + sizeof(MachInst));
134 return target;
135 }
136
137 MipsISA::PCState
138 Jump::branchTarget(ThreadContext *tc) const
139 {
140 MipsISA::PCState target = tc->pcState();
141 Addr pc = target.pc();
142 target.advance();
143 target.npc((pc & 0xF0000000) | disp);
144 target.nnpc(target.npc() + sizeof(MachInst));
145 return target;
146 }
147
148 const std::string &
149 PCDependentDisassembly::disassemble(Addr pc,
150 const SymbolTable *symtab) const
151 {
152 if (!cachedDisassembly ||
153 pc != cachedPC || symtab != cachedSymtab)

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220 printReg(ss, _srcRegIdx[1]);
221 }
222
223 return ss.str();
224 }
225}};
226
227def format Branch(code, *opt_flags) {{
228 not_taken_code = ''
229
230 #Build Instruction Flags
231 #Use Link & Likely Flags to Add Link/Condition Code
232 inst_flags = ('IsDirectControl', )
233 for x in opt_flags:
234 if x == 'Link':
235 code += 'R31 = pc.nnpc();\n'
236 elif x == 'Likely':
237 not_taken_code = 'pc.advance();'
238 inst_flags += ('IsCondDelaySlot', )
239 else:
240 inst_flags += (x, )
241
242 #Take into account uncond. branch instruction
243 if 'cond = 1' in code:
244 inst_flags += ('IsUncondControl', )
245 else:
246 inst_flags += ('IsCondControl', )
247
248 #Condition code
249 code = '''
250 bool cond;
251 MipsISA::PCState pc = PCS;
252 %(code)s
253 if (cond) {
254 pc.nnpc(pc.npc() + disp);
255 } else {
256 %(not_taken_code)s
257 }
258 PCS = pc;
259 ''' % { "code" : code, "not_taken_code" : not_taken_code }
260
261 iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
262 header_output = BasicDeclare.subst(iop)
263 decoder_output = BasicConstructor.subst(iop)
264 decode_block = BasicDecode.subst(iop)
265 exec_output = BasicExecute.subst(iop)
266}};
267
268def format DspBranch(code, *opt_flags) {{
269 not_taken_code = ''
270
271 #Build Instruction Flags
272 #Use Link & Likely Flags to Add Link/Condition Code
273 inst_flags = ('IsDirectControl', )
274 for x in opt_flags:
275 if x == 'Link':
276 code += 'R32 = pc.nnpc();'
277 elif x == 'Likely':
278 not_taken_code = 'pc.advance();'
279 inst_flags += ('IsCondDelaySlot', )
280 else:
281 inst_flags += (x, )
282
283 #Take into account uncond. branch instruction
284 if 'cond = 1' in code:
285 inst_flags += ('IsUncondControl', )
286 else:
287 inst_flags += ('IsCondControl', )
288
289 #Condition code
290 code = '''
291 MipsISA::PCState pc = PCS;
292 bool cond;
293 uint32_t dspctl = DSPControl;
294 %(code)s
295 if (cond) {
296 pc.nnpc(pc.npc() + disp);
297 } else {
298 %(not_taken_code)s
299 }
300 PCS = pc;
301 ''' % { "code" : code, "not_taken_code" : not_taken_code }
302
303 iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
304 header_output = BasicDeclare.subst(iop)
305 decoder_output = BasicConstructor.subst(iop)
306 decode_block = BasicDecode.subst(iop)
307 exec_output = BasicExecute.subst(iop)
308}};
309
310def format Jump(code, *opt_flags) {{
311 #Build Instruction Flags
312 #Use Link Flag to Add Link Code
313 inst_flags = ('IsIndirectControl', 'IsUncondControl')
314 for x in opt_flags:
315 if x == 'Link':
316 code = '''
317 R31 = pc.nnpc();
318 ''' + code
319 elif x == 'ClearHazards':
320 code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
321 else:
322 inst_flags += (x, )
323
324 code = '''
325 MipsISA::PCState pc = PCS;
326 ''' + code
327
328 iop = InstObjParams(name, Name, 'Jump', code, inst_flags)
329 header_output = BasicDeclare.subst(iop)
330 decoder_output = BasicConstructor.subst(iop)
331 decode_block = BasicDecode.subst(iop)
332 exec_output = BasicExecute.subst(iop)
333}};
334
335
336
337