1// -*- mode:c++ -*-
2
3////////////////////////////////////////////////////////////////////
4//
5// Control transfer instructions
6//
7
8output header {{

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63
64 Addr branchTarget(Addr branchPC) const;
65
66 std::string
67 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
68 };
69
70 /**
71 * Base class for jumps (register-indirect control transfers). In
72 * the Mips ISA, these are always unconditional.
73 */
74 class Jump : public PCDependentDisassembly
75 {
76 protected:
77
78 /// Displacement to target address (signed).

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98output decoder {{
99 Addr
100 Branch::branchTarget(Addr branchPC) const
101 {
102 return branchPC + 4 + disp;
103 }
104
105 Addr
106 Jump::branchTarget(ExecContext *xc) const
107 {
108 Addr NPC = xc->readPC() + 4;
109 uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
110 return (Rb & ~3) | (NPC & 1);
111 }
112
113 const std::string &

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137 ccprintf(ss, "%-10s ", mnemonic);
138
139 // There's only one register arg (RA), but it could be
140 // either a source (the condition for conditional
141 // branches) or a destination (the link reg for
142 // unconditional branches)
143 if (_numSrcRegs == 1) {
144 printReg(ss, _srcRegIdx[0]);
145 ss << ", ";
146 } else if(_numSrcRegs == 2) {
147 printReg(ss, _srcRegIdx[0]);
148 ss << ", ";
149 printReg(ss, _srcRegIdx[1]);
150 ss << ", ";
151 }
152
153 Addr target = pc + 4 + disp;
154
155 std::string str;
156 if (symtab && symtab->findSymbol(target, str))
157 ss << str;
158 else
159 ccprintf(ss, "0x%x", target);
160
161 return ss.str();
162 }
163
164 std::string
165 Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
166 {
167 std::stringstream ss;
168
169 ccprintf(ss, "%-10s ", mnemonic);
170
171 if ( mnemonic == "jal" ) {
172 Addr npc = pc + 4;
173 ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
174 } else if (_numSrcRegs == 0) {
175 std::string str;
176 if (symtab && symtab->findSymbol(disp, str))
177 ss << str;
178 else
179 ccprintf(ss, "0x%x", disp);
180 } else if (_numSrcRegs == 1) {
181 printReg(ss, _srcRegIdx[0]);
182 } else if(_numSrcRegs == 2) {
183 printReg(ss, _srcRegIdx[0]);
184 ss << ", ";
185 printReg(ss, _srcRegIdx[1]);
186 }
187
188 return ss.str();
189 }
190}};
191
192def format Branch(code,*opt_flags) {{
193 not_taken_code = ' NNPC = NNPC;\n'
194 not_taken_code += '} \n'
195
196 #Build Instruction Flags
197 #Use Link & Likely Flags to Add Link/Condition Code
198 inst_flags = ('IsDirectControl', )
199 for x in opt_flags:
200 if x == 'Link':
201 code += 'R31 = NNPC;\n'
202 elif x == 'Likely':
203 not_taken_code = ' NPC = NNPC;\n'
204 not_taken_code += ' NNPC = NNPC + 4;\n'
205 not_taken_code += '} \n'
206 inst_flags = ('IsCondDelaySlot', )
207 else:
208 inst_flags += (x, )
209
210 if 'cond == 1' in code:
211 inst_flags += ('IsCondControl', )
212 else:
213 inst_flags += ('IsUncondControl', )
214
215 #Condition code
216 code = 'bool cond;\n' + code
217 code += 'if (cond) {\n'
218 code += ' NNPC = NPC + disp;\n'
219 code += '} else {\n'
220 code += not_taken_code
221
222 iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), inst_flags)
223 header_output = BasicDeclare.subst(iop)
224 decoder_output = BasicConstructor.subst(iop)
225 decode_block = BasicDecode.subst(iop)
226 exec_output = BasicExecute.subst(iop)
227}};
228
229def format Jump(code, *opt_flags) {{
230 #Build Instruction Flags
231 #Use Link Flag to Add Link Code
232 inst_flags = ('IsIndirectControl', 'IsUncondControl')
233 for x in opt_flags:
234 if x == 'Link':
235 code = 'R31 = NNPC;\n' + code
236 elif x == 'ClearHazards':
237 code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
238 else:
239 inst_flags += (x, )
240
241 iop = InstObjParams(name, Name, 'Jump', CodeBlock(code), inst_flags)
242 header_output = BasicDeclare.subst(iop)
243 decoder_output = BasicConstructor.subst(iop)
244 decode_block = BasicDecode.subst(iop)
245 exec_output = BasicExecute.subst(iop)
246}};
247
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250